Charutosh Dixit

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Sunnyvale, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Driver waveform modeling with multiple effective capacitances
- Patent number 6,845,348
- Issue date Jan 18, 2005
- LSI Logic Corporation
- Prasad Subbarao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for checking for power errors in ASIC designs
- Patent number 6,829,754
- Issue date Dec 7, 2004
- LSI Logic Corporation
- Qiong J. Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Capacitance estimation
- Patent number 6,542,834
- Issue date Apr 1, 2003
- LSI Logic Corporation
- Charutosh Dixit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
4K derating scheme for propagation delay and setup/hold time comput...
- Patent number 6,484,297
- Issue date Nov 19, 2002
- LSI Logic Corporation
- Charutosh Dixit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pin placement method for integrated circuits
- Patent number 6,449,760
- Issue date Sep 10, 2002
- LSI Logic Corporation
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Pin placement method for integrated circuits
- Publication number 20020066066
- Publication date May 30, 2002
- Alexander Tetelbaum
- G06 - COMPUTING CALCULATING COUNTING