Chatterjee Niladrish

Person

Salt Lake City, UT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Combined on-package and off-package memory system
- Patent number 12,001,725
- Issue date Jun 4, 2024
- NVIDIA Corporation
- Niladrish Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined on-package and off-package memory system
- Patent number 11,789,649
- Issue date Oct 17, 2023
- NVIDIA Corporation
- Niladrish Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for configuring parallel processors for different applic...
- Patent number 11,609,879
- Issue date Mar 21, 2023
- NVIDIA Corporation
- Yaosheng Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for dynamic random access memory (DRAM) sub-cha...
- Patent number 10,468,093
- Issue date Nov 5, 2019
- NVIDIA Corporation
- Niladrish Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Page migration in a hybrid memory device
- Patent number 9,910,605
- Issue date Mar 6, 2018
- Advanced Micro Devices, Inc.
- Nuwan S. Jayasena
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access methods and apparatus
- Patent number 9,846,550
- Issue date Dec 19, 2017
- Hewlett Packard Enterprise Development LP
- Naveen Muralimanohar
- G11 - INFORMATION STORAGE
Information Patent Grant
Page migration in a 3D stacked hybrid memory
- Patent number 9,535,831
- Issue date Jan 3, 2017
- Advanced Micro Devices, Inc.
- Nuwan S. Jayasena
- G11 - INFORMATION STORAGE
Information Patent Grant
Scheduling memory accesses using an efficient row burst value
- Patent number 9,489,321
- Issue date Nov 8, 2016
- Advanced Micro Devices, Inc.
- James M. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access methods and apparatus
- Patent number 9,361,955
- Issue date Jun 7, 2016
- Hewlett Packard Enterprise Development LP
- Naveen Muralimanohar
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
COMPUTATION OFFLOAD REQUESTS WITH DENIAL RESPONSE
- Publication number 20240281300
- Publication date Aug 22, 2024
- NVIDIA Corporation
- Donghyuk Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PAGE ACCESS INSTRUMENTATION
- Publication number 20240256153
- Publication date Aug 1, 2024
- NVIDIA Corporation
- Niladrish Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMBINED ON-PACKAGE AND OFF-PACKAGE MEMORY SYSTEM
- Publication number 20220342595
- Publication date Oct 27, 2022
- NVIDIA Corporation
- Niladrish Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR CONFIGURING PARALLEL PROCESSORS FOR DIFFERENT APPLIC...
- Publication number 20220276984
- Publication date Sep 1, 2022
- NVIDIA Corporation
- Yaosheng FU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) SUB-CHA...
- Publication number 20170255552
- Publication date Sep 7, 2017
- NVIDIA Corporation
- Niladrish Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PAGE MIGRATION IN A 3D STACKED HYBRID MEMORY
- Publication number 20170160955
- Publication date Jun 8, 2017
- Advanced Micro Devices, Inc.
- Nuwan S. Jayasena
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Access Methods And Apparatus
- Publication number 20160216912
- Publication date Jul 28, 2016
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Naveen Muralimanohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PAGE MIGRATION IN A 3D STACKED HYBRID MEMORY
- Publication number 20150199126
- Publication date Jul 16, 2015
- Advanced Micro Devices, Inc.
- Nuwan S. Jayasena
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCHEDULING MEMORY ACCESSES USING AN EFFICIENT ROW BURST VALUE
- Publication number 20140372711
- Publication date Dec 18, 2014
- James M. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ACCESS METHODS AND APPARATUS
- Publication number 20140208156
- Publication date Jul 24, 2014
- Naveen Muralimanohar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTER-ROW DATA TRANSFER IN MEMORY DEVICES
- Publication number 20140177347
- Publication date Jun 26, 2014
- Advanced Micro Devices, Inc.
- Niladrish Chatterjee
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCING MEMORY ACCESS TIME IN PARALLEL PROCESSORS
- Publication number 20140173225
- Publication date Jun 19, 2014
- Advanced Micro Devices, Inc.
- Niladrish Chatterjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE SUBARRAY MEMORY ACCESS
- Publication number 20140173170
- Publication date Jun 19, 2014
- Hewlett-Packard Development Company, L.P.
- Naveen Muralimanohar
- G06 - COMPUTING CALCULATING COUNTING

Chatterjee Niladrish

Person

Patents Grantslast 30 patents

Combined on-package and off-package memory system

Combined on-package and off-package memory system

Techniques for configuring parallel processors for different applic...

Systems and methods for dynamic random access memory (DRAM) sub-cha...

Page migration in a hybrid memory device

Memory access methods and apparatus

Page migration in a 3D stacked hybrid memory

Scheduling memory accesses using an efficient row burst value

Memory access methods and apparatus

Patents Applicationslast 30 patents

COMPUTATION OFFLOAD REQUESTS WITH DENIAL RESPONSE

MEMORY PAGE ACCESS INSTRUMENTATION

COMBINED ON-PACKAGE AND OFF-PACKAGE MEMORY SYSTEM

TECHNIQUES FOR CONFIGURING PARALLEL PROCESSORS FOR DIFFERENT APPLIC...

SYSTEMS AND METHODS FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) SUB-CHA...

PAGE MIGRATION IN A 3D STACKED HYBRID MEMORY

Memory Access Methods And Apparatus

PAGE MIGRATION IN A 3D STACKED HYBRID MEMORY

SCHEDULING MEMORY ACCESSES USING AN EFFICIENT ROW BURST VALUE

MEMORY ACCESS METHODS AND APPARATUS

INTER-ROW DATA TRANSFER IN MEMORY DEVICES

REDUCING MEMORY ACCESS TIME IN PARALLEL PROCESSORS

MULTIPLE SUBARRAY MEMORY ACCESS