Chau-Chin Wu

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for CAM with reduced cross-coupling interference
- Patent number 7,859,876
- Issue date Dec 28, 2010
- Netlogic Microsystems, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
CAM arrays having CAM cells therein with match line and low match l...
- Patent number RE41351
- Issue date May 25, 2010
- NetLogic Microsystems, Inc.
- Chuen-Der Lien
- 365 - Static information storage and retrieval
Information Patent Grant
Method and apparatus for CAM with reduced cross-coupling interference
- Patent number 7,545,660
- Issue date Jun 9, 2009
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for CAM with reduced cross-coupling interference
- Patent number 7,522,438
- Issue date Apr 21, 2009
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for integrated circuit charge recycling
- Patent number 7,414,460
- Issue date Aug 19, 2008
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Reduced size dual-port SRAM cell
- Patent number 7,359,275
- Issue date Apr 15, 2008
- Integrated Device Technology, Inc.
- Chau-Chin Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory (CAM) devices that support background BI...
- Patent number 7,304,875
- Issue date Dec 4, 2007
- Integrated Device Technology Inc.
- Chuen Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for CAM with reduced cross-coupling interference
- Patent number 7,248,492
- Issue date Jul 24, 2007
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for CAM with reduced cross-coupling interference
- Patent number 7,187,571
- Issue date Mar 6, 2007
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory (CAM) arrays and cells having low power...
- Patent number RE39227
- Issue date Aug 8, 2006
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- 365 - Static information storage and retrieval
Information Patent Grant
Content addressable memory (CAM) devices having scalable multiple m...
- Patent number 6,924,994
- Issue date Aug 2, 2005
- Integrated Device Technology, Inc.
- James K. Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory (CAM) devices having error detection and...
- Patent number 6,879,504
- Issue date Apr 12, 2005
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple match detection logic and gates for content addressable me...
- Patent number 6,859,378
- Issue date Feb 22, 2005
- Integrated Device Technology, Inc.
- James K. Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory (CAM) devices that utilize multi-port CA...
- Patent number 6,781,857
- Issue date Aug 24, 2004
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
ESD protection circuit
- Patent number 6,724,601
- Issue date Apr 20, 2004
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cam circuit with separate memory and logic operating voltages
- Patent number 6,661,687
- Issue date Dec 9, 2003
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Content addressable memory (CAM) devices having reliable column red...
- Patent number 6,657,878
- Issue date Dec 2, 2003
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM circuit with separate refresh memory
- Patent number 6,563,754
- Issue date May 13, 2003
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
CAM circuit with separate memory and logic operating voltages
- Patent number 6,512,685
- Issue date Jan 28, 2003
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Increasing priority encoder speed using the most significant bit of...
- Patent number 6,505,271
- Issue date Jan 7, 2003
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelining a content addressable memory cell array for low-power op...
- Patent number 6,470,418
- Issue date Oct 22, 2002
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM-based CAM cell using 3T or 4T DRAM cells
- Patent number 6,421,265
- Issue date Jul 16, 2002
- Integrated Devices Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Ternary CAM cell with DRAM mask circuit
- Patent number 6,400,593
- Issue date Jun 4, 2002
- Intregrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Level-shifting signal buffers that support higher voltage power sup...
- Patent number 6,388,499
- Issue date May 14, 2002
- Integrated Device Technology, Inc.
- Ta-Ke Tien
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Quad CAM cell with minimum cell size
- Patent number 6,373,739
- Issue date Apr 16, 2002
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
CAM array with minimum cell size
- Patent number 6,266,263
- Issue date Jul 24, 2001
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Ternary CAM array
- Patent number 6,262,907
- Issue date Jul 17, 2001
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Cam array with minimum cell size
- Patent number 6,256,216
- Issue date Jul 3, 2001
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge pump for improving memory cell low VCC performance without i...
- Patent number 6,215,708
- Issue date Apr 10, 2001
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Five-transistor SRAM cell
- Patent number 6,205,049
- Issue date Mar 20, 2001
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CAM CIRCUIT WITH SEPARATE MEMORY AND LOGIC OPERATING VOLTAGES
- Publication number 20030227789
- Publication date Dec 11, 2003
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Application
Content addressable memory (CAM) devices having reliable column red...
- Publication number 20030165073
- Publication date Sep 4, 2003
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Application
ESD protection circuit
- Publication number 20020131221
- Publication date Sep 19, 2002
- Chuen-Der Lien
- H01 - BASIC ELECTRIC ELEMENTS

Chau-Chin Wu

Person

Patents Grantslast 30 patents

Method and apparatus for CAM with reduced cross-coupling interference

CAM arrays having CAM cells therein with match line and low match l...

Method and apparatus for CAM with reduced cross-coupling interference

Method and apparatus for CAM with reduced cross-coupling interference

System and method for integrated circuit charge recycling

Reduced size dual-port SRAM cell

Content addressable memory (CAM) devices that support background BI...

Method and apparatus for CAM with reduced cross-coupling interference

Method and apparatus for CAM with reduced cross-coupling interference

Content addressable memory (CAM) arrays and cells having low power...

Content addressable memory (CAM) devices having scalable multiple m...

Content addressable memory (CAM) devices having error detection and...

Multiple match detection logic and gates for content addressable me...

Content addressable memory (CAM) devices that utilize multi-port CA...

ESD protection circuit

Cam circuit with separate memory and logic operating voltages

Content addressable memory (CAM) devices having reliable column red...

DRAM circuit with separate refresh memory

CAM circuit with separate memory and logic operating voltages

Increasing priority encoder speed using the most significant bit of...

Pipelining a content addressable memory cell array for low-power op...

DRAM-based CAM cell using 3T or 4T DRAM cells

Ternary CAM cell with DRAM mask circuit

Level-shifting signal buffers that support higher voltage power sup...

Quad CAM cell with minimum cell size

CAM array with minimum cell size

Ternary CAM array

Cam array with minimum cell size

Charge pump for improving memory cell low VCC performance without i...

Five-transistor SRAM cell

Patents Applicationslast 30 patents

CAM CIRCUIT WITH SEPARATE MEMORY AND LOGIC OPERATING VOLTAGES

Content addressable memory (CAM) devices having reliable column red...

ESD protection circuit