Chauchin Su

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Taipei City, TW

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Patents Grantslast 30 patents

Information Patent Grant
Method and system for layout parasitic estimation
- Patent number 8,806,414
- Issue date Aug 12, 2014
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Mu-Jen Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-the-fly device characterization from layouts of circuits
- Patent number 8,726,207
- Issue date May 13, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yu-Sian Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IEEE Std. 1149.4 compatible analog BIST methodology
- Patent number 7,228,479
- Issue date Jun 5, 2007
- Syntest Technologies, Inc.
- Chauchin Su
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR LAYOUT PARASITIC ESTIMATION
- Publication number 20130326447
- Publication date Dec 5, 2013
- Taiwan Semiconductor Manufacturing Co., LTD
- Mu-Jen HUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-the-Fly Device Characterization from Layouts of Circuits
- Publication number 20120304146
- Publication date Nov 29, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yu-Sian Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IEEE Std. 1149.4 compatible analog BIST methodology
- Publication number 20060059395
- Publication date Mar 16, 2006
- Chauchin Su
- G01 - MEASURING TESTING