Che-Jen Hu

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Laminated stress overlayer using In-situ multiple plasma treatments...
- Patent number 8,114,784
- Issue date Feb 14, 2012
- Texas Instruments Incorporated
- Haowen Bu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Methods to selectively protect NMOS regions, PMOS regions, and gate...
- Patent number 7,514,309
- Issue date Apr 7, 2009
- Texas Instruments Incorporated
- Seetharaman Sridhar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor with a nitrided silicon gate oxide and method
- Patent number 6,956,267
- Issue date Oct 18, 2005
- Texas Instruments Incorporated
- Sunil V. Hattangady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of MOS transistor having increased substrate r...
- Patent number 6,764,909
- Issue date Jul 20, 2004
- Texas Instruments Incorporated
- Craig T. Salling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Complementary transistors with controlled drain extension overlap
- Patent number 6,730,556
- Issue date May 4, 2004
- Texas Instruments Incorporated
- Zhiqiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor with a nitrided silicon gate oxide and method
- Patent number 6,716,695
- Issue date Apr 6, 2004
- Texas Instruments Incorporated
- Sunil V. Hattangady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layered polysilicon process
- Patent number 6,645,840
- Issue date Nov 11, 2003
- Texas Instruments Incorporated
- Douglas T. Grider
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of MOS transistor having increased substrate r...
- Patent number 6,627,955
- Issue date Sep 30, 2003
- Texas Instruments Incorporated
- Craig T. Salling
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Methods to selectively protect NMOS regions, PMOS regions, and gate...
- Publication number 20070020839
- Publication date Jan 25, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Seetharaman Sridhar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor with a nitrided silicon gate oxide and method
- Publication number 20040159898
- Publication date Aug 19, 2004
- Sunil V. Hattangady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and method of MOS transistor having increased substrate r...
- Publication number 20030207543
- Publication date Nov 6, 2003
- Craig T. Salling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device and method
- Publication number 20030143813
- Publication date Jul 31, 2003
- TEXAS INSTRUMENTS INCORPORATED
- Rajesh B. Khamankar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Complementary transistors with controlled drain extension overlap
- Publication number 20030107104
- Publication date Jun 12, 2003
- Zhiqiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and method of MOS transistor having increased substrate r...
- Publication number 20020096716
- Publication date Jul 25, 2002
- Craig T. Salling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-layered polysilicon process
- Publication number 20020048918
- Publication date Apr 25, 2002
- Douglas T. Grider
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Laminated stress overlayer using In-situ multiple plasma treatments...

Methods to selectively protect NMOS regions, PMOS regions, and gate...

Semiconductor with a nitrided silicon gate oxide and method

Structure and method of MOS transistor having increased substrate r...

Complementary transistors with controlled drain extension overlap

Semiconductor with a nitrided silicon gate oxide and method

Multi-layered polysilicon process

Structure and method of MOS transistor having increased substrate r...

Patents Applicationslast 30 patents

Methods to selectively protect NMOS regions, PMOS regions, and gate...

Semiconductor with a nitrided silicon gate oxide and method

Structure and method of MOS transistor having increased substrate r...

Semiconductor device and method

Complementary transistors with controlled drain extension overlap

Structure and method of MOS transistor having increased substrate r...

Multi-layered polysilicon process