Chee Seng Foong

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Packaged semiconductor device assembly
- Patent number 11,908,784
- Issue date Feb 20, 2024
- NXP USA, INC.
- Akhilesh Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device package substrate structure and method therefor
- Patent number 11,798,871
- Issue date Oct 24, 2023
- NXP USA, INC.
- Chee Seng Foong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with conductive underfill ground plane
- Patent number 11,270,972
- Issue date Mar 8, 2022
- NXP B.V.
- Nishant Lakhera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid package
- Patent number 11,189,557
- Issue date Nov 30, 2021
- NXP USA, INC.
- Akhilesh Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating embedded traces
- Patent number 11,018,024
- Issue date May 25, 2021
- NXP USA, INC.
- Trent Uehling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro-selective sintering laser systems and methods thereof
- Patent number 10,722,947
- Issue date Jul 28, 2020
- Board of Regents, The University of Texas System
- Michael A. Cullinan
- B22 - CASTING POWDER METALLURGY
Information Patent Grant
Substrate dielectric crack prevention using interleaved metal plane
- Patent number 10,537,019
- Issue date Jan 14, 2020
- NXP USA, INC.
- Tingdong Zhou
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Substrate interconnections for packaged semiconductor device
- Patent number 9,997,445
- Issue date Jun 12, 2018
- NXP USA, INC.
- Kai Yun Yow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged semiconductor device having a lead frame and inner and out...
- Patent number 9,978,669
- Issue date May 22, 2018
- NXP USA, INC.
- Chee Seng Foong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Laser sintered interconnections between die
- Patent number 9,935,079
- Issue date Apr 3, 2018
- NXP USA, INC.
- Chee Seng Foong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Universal BGA substrate
- Patent number 9,698,093
- Issue date Jul 4, 2017
- NXP USA,INC.
- Chee Seng Foong
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
DEVICE PACKAGE SUBSTRATE STRUCTURE AND METHOD THEREFOR
- Publication number 20240014114
- Publication date Jan 11, 2024
- NXP USA, Inc.
- Chee Seng Foong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKING A SEMICONDUCTOR DIE AND CHIP-SCALE-PACKAGE UNIT
- Publication number 20230137977
- Publication date May 4, 2023
- NXP B.V.
- Akhilesh Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED SEMICONDUCTOR DEVICE ASSEMBLY
- Publication number 20220093499
- Publication date Mar 24, 2022
- NXP USA, Inc.
- Akhilesh Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE PACKAGE SUBSTRATE STRUCTURE AND METHOD THEREFOR
- Publication number 20220059441
- Publication date Feb 24, 2022
- NXP USA, Inc.
- Chee Seng Foong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH CONDUCTIVE UNDERFILL GROUND PLANE
- Publication number 20200395332
- Publication date Dec 17, 2020
- NXP USA, Inc.
- Nishant Lakhera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID PACKAGE
- Publication number 20200185319
- Publication date Jun 11, 2020
- NXP USA, Inc.
- Akhilesh Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE WITH EMBEDDED TRACES
- Publication number 20200043750
- Publication date Feb 6, 2020
- NXP USA, Inc.
- Trent Uehling
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID PACKAGE
- Publication number 20200013711
- Publication date Jan 9, 2020
- NXP USA, Inc.
- Akhilesh Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE INTERCONNECTIONS FOR PACKAGED SEMICONDUCTOR DEVICE
- Publication number 20180114748
- Publication date Apr 26, 2018
- NXP USA, Inc.
- Kai Yun Yow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICRO-SELECTIVE SINTERING LASER SYSTEMS AND METHODS THEREOF
- Publication number 20180065186
- Publication date Mar 8, 2018
- Board of Regents, The University of Texas System
- Michael A. Cullinan
- B33 - ADDITIVE MANUFACTURING TECHNOLOGY
Information Patent Application
PACKAGED SEMICONDUCTOR DEVICE HAVING A LEAD FRAME AND INNER AND OUT...
- Publication number 20180005925
- Publication date Jan 4, 2018
- FREESCALE SEMICONDUCTOR, INC.
- CHEE SENG FOONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH ON-DIE POWER DISTRIBUTION BARS
- Publication number 20170062311
- Publication date Mar 2, 2017
- FREESCALE SEMICONDUCTOR, INC.
- Chee Seng Foong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
UNIVERSAL BGA SUBSTRATE
- Publication number 20170062320
- Publication date Mar 2, 2017
- FREESCALE SEMICONDUCTOR, INC.
- CHEE SENG FOONG
- H01 - BASIC ELECTRIC ELEMENTS

Chee Seng Foong

Person

Patents Grantslast 30 patents

Packaged semiconductor device assembly

Device package substrate structure and method therefor

Package with conductive underfill ground plane

Hybrid package

Method of fabricating embedded traces

Micro-selective sintering laser systems and methods thereof

Substrate dielectric crack prevention using interleaved metal plane

Substrate interconnections for packaged semiconductor device

Packaged semiconductor device having a lead frame and inner and out...

Laser sintered interconnections between die

Universal BGA substrate

Patents Applicationslast 30 patents

DEVICE PACKAGE SUBSTRATE STRUCTURE AND METHOD THEREFOR

STACKING A SEMICONDUCTOR DIE AND CHIP-SCALE-PACKAGE UNIT

PACKAGED SEMICONDUCTOR DEVICE ASSEMBLY

DEVICE PACKAGE SUBSTRATE STRUCTURE AND METHOD THEREFOR

PACKAGE WITH CONDUCTIVE UNDERFILL GROUND PLANE

HYBRID PACKAGE

SUBSTRATE WITH EMBEDDED TRACES

HYBRID PACKAGE

SUBSTRATE INTERCONNECTIONS FOR PACKAGED SEMICONDUCTOR DEVICE

MICRO-SELECTIVE SINTERING LASER SYSTEMS AND METHODS THEREOF

PACKAGED SEMICONDUCTOR DEVICE HAVING A LEAD FRAME AND INNER AND OUT...

INTEGRATED CIRCUIT WITH ON-DIE POWER DISTRIBUTION BARS

UNIVERSAL BGA SUBSTRATE