Chen-Chi Kuo

Person

Pleasanton, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method to merge and align data from distributed memor...
- Patent number 8,370,558
- Issue date Feb 5, 2013
- Intel Corporation
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for scheduling the processing of commands for...
- Patent number 8,065,678
- Issue date Nov 22, 2011
- Intel Corporation
- Jaroslaw J. Sydir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for two-stage packet classification using most...
- Patent number 7,525,958
- Issue date Apr 28, 2009
- Intel Corporation
- Alok Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for scheduling the processing of commands for...
- Patent number 7,512,945
- Issue date Mar 31, 2009
- Intel Corporation
- Jaroslaw J. Sydir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to merge and align data from distributed memor...
- Patent number 7,480,781
- Issue date Jan 20, 2009
- Intel Corporation
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Engine for comparing a key with rules having high and low values de...
- Patent number 7,340,570
- Issue date Mar 4, 2008
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus to handle parity errors in flow control channels
- Patent number 7,337,371
- Issue date Feb 26, 2008
- Intel Corporation
- Chen-Chi Kuo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Processing element with next and previous neighbor registers for di...
- Patent number 7,275,145
- Issue date Sep 25, 2007
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus utilizing non-uniformly distributed DRAM confi...
- Patent number 7,213,099
- Issue date May 1, 2007
- Intel Corporation
- Chen-Chi Kuo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller for padding and stripping data in response to rea...
- Patent number 7,210,008
- Issue date Apr 24, 2007
- Intel Corporation
- Prashant R. Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet assembly
- Patent number 7,185,153
- Issue date Feb 27, 2007
- Intel Corporation
- Prashant R. Chandra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Network packet buffer allocation optimization in memory bank systems
- Patent number 7,158,438
- Issue date Jan 2, 2007
- Intel Corporation
- Chen-Chi Kuo
- G11 - INFORMATION STORAGE
Information Patent Grant
Network packet buffer allocation optimization in memory bank systems
- Patent number 6,906,980
- Issue date Jun 14, 2005
- Intel Corporation
- Chen-Chi Kuo
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR SCHEDULING THE PROCESSING OF COMMANDS FOR...
- Publication number 20120060159
- Publication date Mar 8, 2012
- Intel Corporation
- Jaroslaw J. Sydir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for scheduling the processing of commands for...
- Publication number 20090271795
- Publication date Oct 29, 2009
- Jaroslaw J. Sydir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD TO MERGE AND ALIGN DATA FROM DISTRIBUTED MEMOR...
- Publication number 20090132773
- Publication date May 21, 2009
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method to merge and align data from distributed memor...
- Publication number 20060149872
- Publication date Jul 6, 2006
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Engine for comparing a key with rules having defined ranges
- Publication number 20060041725
- Publication date Feb 23, 2006
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Apparatus and method for two-stage packet classification using most...
- Publication number 20050226235
- Publication date Oct 13, 2005
- Alok Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Network packet buffer allocation optimization in memory bank systems
- Publication number 20050169092
- Publication date Aug 4, 2005
- Chen-Chi Kuo
- G11 - INFORMATION STORAGE
Information Patent Application
Processing element with next and previous neighbor registers
- Publication number 20050149691
- Publication date Jul 7, 2005
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus utilizing non-uniformly distributed DRAM confi...
- Publication number 20050144413
- Publication date Jun 30, 2005
- Chen-Chi Kuo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for scheduling the processing of commands for...
- Publication number 20050141715
- Publication date Jun 30, 2005
- Jaroslaw J. Sydir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to handle parity errors in flow control channels
- Publication number 20050141535
- Publication date Jun 30, 2005
- Chen-Chi Kuo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Packet assembly
- Publication number 20050135353
- Publication date Jun 23, 2005
- Prashant R. Chandra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Memory controller
- Publication number 20050135367
- Publication date Jun 23, 2005
- Prashant R. Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Locally stored portion of a calendar structure indicating when inte...
- Publication number 20050128948
- Publication date Jun 16, 2005
- Chen-Chi Kuo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Preventing a packet associated with a blocked port from being place...
- Publication number 20050128945
- Publication date Jun 16, 2005
- Chen-Chi Kuo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Executing instructions on a processor
- Publication number 20050050306
- Publication date Mar 3, 2005
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and process for scheduling data packet collection
- Publication number 20040252687
- Publication date Dec 16, 2004
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Network packet buffer allocation optimization in memory bank systems
- Publication number 20040130961
- Publication date Jul 8, 2004
- Chen-Chi Kuo
- G11 - INFORMATION STORAGE

Chen-Chi Kuo

Person

Patents Grantslast 30 patents

Apparatus and method to merge and align data from distributed memor...

Method and apparatus for scheduling the processing of commands for...

Apparatus and method for two-stage packet classification using most...

Method and apparatus for scheduling the processing of commands for...

Apparatus and method to merge and align data from distributed memor...

Engine for comparing a key with rules having high and low values de...

Method and apparatus to handle parity errors in flow control channels

Processing element with next and previous neighbor registers for di...

Method and apparatus utilizing non-uniformly distributed DRAM confi...

Memory controller for padding and stripping data in response to rea...

Packet assembly

Network packet buffer allocation optimization in memory bank systems

Network packet buffer allocation optimization in memory bank systems

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR SCHEDULING THE PROCESSING OF COMMANDS FOR...

Method and apparatus for scheduling the processing of commands for...

APPARATUS AND METHOD TO MERGE AND ALIGN DATA FROM DISTRIBUTED MEMOR...

Apparatus and method to merge and align data from distributed memor...

Engine for comparing a key with rules having defined ranges

Apparatus and method for two-stage packet classification using most...

Network packet buffer allocation optimization in memory bank systems

Processing element with next and previous neighbor registers

Method and apparatus utilizing non-uniformly distributed DRAM confi...

Method and apparatus for scheduling the processing of commands for...

Method and apparatus to handle parity errors in flow control channels

Packet assembly

Memory controller

Locally stored portion of a calendar structure indicating when inte...

Preventing a packet associated with a blocked port from being place...

Executing instructions on a processor

Method and process for scheduling data packet collection

Network packet buffer allocation optimization in memory bank systems