Chen Koren

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Folsom, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for implement a multi-level memory hierarchy
- Patent number 9,448,879
- Issue date Sep 20, 2016
- Intel Corporation
- Theodros Yigzaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level tracking of in-use state of cache lines
- Patent number 9,348,591
- Issue date May 24, 2016
- Intel Corporation
- Ilhyun Kim
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENT A MULTI-LEVEL MEMORY HIERARCHY
- Publication number 20140298140
- Publication date Oct 2, 2014
- Theodros Yigzaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL TRACKING OF IN-USE STATE OF CACHE LINES
- Publication number 20130275733
- Publication date Oct 17, 2013
- Ilhyun Kim
- G06 - COMPUTING CALCULATING COUNTING