Chen W. Tseng

Person

Longmont, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit network with an error detection system for mitigation of er...
- Patent number 9,436,562
- Issue date Sep 6, 2016
- Xilinx, Inc.
- Matthew H. Klein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for fault injection and verification on an int...
- Patent number 9,208,043
- Issue date Dec 8, 2015
- Xilinx, Inc.
- Chen W. Tseng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single event upset mitigation
- Patent number 8,922,242
- Issue date Dec 30, 2014
- Xilinx, Inc.
- Chen W. Tseng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Partially programming an integrated circuit using control memory cells
- Patent number 8,786,310
- Issue date Jul 22, 2014
- Xilinx, Inc.
- Weiguang Lu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bit error mitigation
- Patent number 8,713,409
- Issue date Apr 29, 2014
- Xilinx, Inc.
- Chen W. Tseng
- G11 - INFORMATION STORAGE
Information Patent Grant
Power control using global control signal to selected circuitry in...
- Patent number 8,633,730
- Issue date Jan 21, 2014
- Xilinx, Inc.
- Chen W. Tseng
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for single event upset (SEU) detection and cor...
- Patent number 8,635,581
- Issue date Jan 21, 2014
- Xilinx, Inc.
- Chen W. Tseng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-checking and self-correcting internal configuration port circu...
- Patent number 8,099,625
- Issue date Jan 17, 2012
- Xilinx, Inc.
- Chen Wei Tseng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single event upset mitigation
- Patent number 7,990,173
- Issue date Aug 2, 2011
- Xilinx, Inc.
- Chen W. Tseng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Implementing a user design in a programmable logic device with sing...
- Patent number 7,650,585
- Issue date Jan 19, 2010
- Xilinx, Inc.
- Gregory J. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for configuring an integrated circuit
- Patent number 7,626,415
- Issue date Dec 1, 2009
- Xilinx, Inc.
- Chen Wei Tseng
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for configuring an integrated circuit
- Patent number 7,589,558
- Issue date Sep 15, 2009
- Xilinx, Inc.
- Chen Wei Tseng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for mitigating one or more event upsets
- Patent number 7,576,557
- Issue date Aug 18, 2009
- Xilinx, Inc.
- Chen Wei Tseng
- H03 - BASIC ELECTRONIC CIRCUITRY

Chen W. Tseng

Person

Patents Grantslast 30 patents

Circuit network with an error detection system for mitigation of er...

Method and apparatus for fault injection and verification on an int...

Single event upset mitigation

Partially programming an integrated circuit using control memory cells

Bit error mitigation

Power control using global control signal to selected circuitry in...

Method and apparatus for single event upset (SEU) detection and cor...

Self-checking and self-correcting internal configuration port circu...

Single event upset mitigation

Implementing a user design in a programmable logic device with sing...

Method and apparatus for configuring an integrated circuit

Method and apparatus for configuring an integrated circuit

Method and apparatus for mitigating one or more event upsets