Cheng-Chung Huang

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Gate-to-gate isolation for stacked transistor architecture via sele...
- Patent number 12,369,399
- Issue date Jul 22, 2025
- Intel Corporation
- Willy Rachmady
Information Patent Grant
Asymmetric gate structures and contacts for stacked transistors
- Patent number 12,342,614
- Issue date Jun 24, 2025
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with isolation below source and drain
- Patent number 12,288,803
- Issue date Apr 29, 2025
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sideways vias in isolation areas to contact interior layers in stac...
- Patent number 12,255,137
- Issue date Mar 18, 2025
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forksheet transistors with dielectric or conductive spine
- Patent number 12,243,875
- Issue date Mar 4, 2025
- Intel Corporation
- Seung Hoon Sung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having depopulated ch...
- Patent number 12,230,635
- Issue date Feb 18, 2025
- Intel Corporation
- Nicole Thomas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming an oxide volume within a fin
- Patent number 12,224,202
- Issue date Feb 11, 2025
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin-film transistors and MIM capacitors in exclusion zones
- Patent number 12,183,668
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek A. Sharma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked source-drain-gate connection and process for forming such
- Patent number 12,148,806
- Issue date Nov 19, 2024
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arrays of double-sided dram cells including capacitors on the front...
- Patent number 12,120,865
- Issue date Oct 15, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect techniques for electrically connecting source/drain re...
- Patent number 12,107,085
- Issue date Oct 1, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance semiconductor oxide material channel regions for NMOS
- Patent number 12,068,319
- Issue date Aug 20, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Epitaxial layer with substantially parallel sides
- Patent number 12,020,929
- Issue date Jun 25, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leave-behind protective layer having secondary purpose
- Patent number 11,996,408
- Issue date May 28, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked forksheet transistors
- Patent number 11,996,411
- Issue date May 28, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional integrated circuits (3DICs) including bottom gate...
- Patent number 11,996,404
- Issue date May 28, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sideways vias in isolation areas to contact interior layers in stac...
- Patent number 11,942,416
- Issue date Mar 26, 2024
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-silicon N-type and P-type stacked transistors for integrated ci...
- Patent number 11,935,891
- Issue date Mar 19, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ferroelectric gate stack for band-to-band tunneling reduction
- Patent number 11,929,435
- Issue date Mar 12, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Top gate recessed channel CMOS thin film transistor in the back end...
- Patent number 11,929,320
- Issue date Mar 12, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forksheet transistors with dielectric or conductive spine
- Patent number 11,923,370
- Issue date Mar 5, 2024
- Intel Corporation
- Seung Hoon Sung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with isolation below source and drain
- Patent number 11,923,410
- Issue date Mar 5, 2024
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked source-drain-gate connection and process for forming such
- Patent number 11,916,118
- Issue date Feb 27, 2024
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked trigate transistors with dielectric isolation and process f...
- Patent number 11,894,372
- Issue date Feb 6, 2024
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin film transistor structures with regrown source and drain
- Patent number 11,887,988
- Issue date Jan 30, 2024
- Intel Corporation
- Ashish Agrawal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical tunneling field-effect transistors
- Patent number 11,862,715
- Issue date Jan 2, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having depopulated ch...
- Patent number 11,862,636
- Issue date Jan 2, 2024
- Intel Corporation
- Nicole Thomas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having depopulated ch...
- Patent number 11,830,933
- Issue date Nov 28, 2023
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Subfin leakage suppression using fixed charge
- Patent number 11,784,239
- Issue date Oct 10, 2023
- Intel Corporation
- Sean T. Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having depopulated ch...
- Patent number 11,764,263
- Issue date Sep 19, 2023
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
CAPPING NANORIBBON FINS IN SUPERLATTICE STRUCTURES DURING FABRICATION
- Publication number 20250212522
- Publication date Jun 26, 2025
- Intel Corporation
- Cheng-Ying Huang
Information Patent Application
FORKSHEET TRANSISTORS WITH DIELECTRIC OR CONDUCTIVE SPINE
- Publication number 20250185363
- Publication date Jun 5, 2025
- Intel Corporation
- Seung Hoon SUNG
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...
- Publication number 20250113603
- Publication date Apr 3, 2025
- Intel Corporation
- Munzarin QAYYUM
Information Patent Application
ARRAYS OF DOUBLE-SIDED DRAM CELLS INCLUDING CAPACITORS ON THE FRONT...
- Publication number 20250031362
- Publication date Jan 23, 2025
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED CMOS TRANSISTOR STRUCTURES WITH COMPLEMENTARY CHANNEL MATER...
- Publication number 20250006737
- Publication date Jan 2, 2025
- Intel Corporation
- Aryan Navabi-Shirazi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED FORKSHEET TRANSISTORS
- Publication number 20240234422
- Publication date Jul 11, 2024
- Intel Corporation
- Cheng-Ying HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNOLOGIES FOR RIBBON FIELD EFFECT TRANSISTORS WITH VARIABLE FIN...
- Publication number 20240222521
- Publication date Jul 4, 2024
- Intel Corporation
- Evan A. Clinton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNOLOGIES FOR RIBBON FIELD EFFECT TRANSISTORS WITH VARIABLE FIN...
- Publication number 20240222376
- Publication date Jul 4, 2024
- Intel Corporation
- Marko Radosavljevic
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANORIBBON STACKS WITHOUT DIELECTRIC PROTECTION CAPS FOR TOP NANORI...
- Publication number 20240204060
- Publication date Jun 20, 2024
- Intel Corporation
- Rohit Galatage
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR GATE-CHANNEL ARRANGEMENTS WITH MULTIPLE DIPOLE MATERIALS
- Publication number 20240204103
- Publication date Jun 20, 2024
- Intel Corporation
- Rohit Galatage
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE CONTACTED SUB-FIN DIODES
- Publication number 20240170581
- Publication date May 23, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STAC...
- Publication number 20240162141
- Publication date May 16, 2024
- Intel Corporation
- Ehren MANNEBACH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORKSHEET TRANSISTORS WITH DIELECTRIC OR CONDUCTIVE SPINE
- Publication number 20240153956
- Publication date May 9, 2024
- Intel Corporation
- Seung Hoon SUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH
- Publication number 20240145557
- Publication date May 2, 2024
- Intel Corporation
- Ehren MANNEBACH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF...
- Publication number 20240136277
- Publication date Apr 25, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN
- Publication number 20240113161
- Publication date Apr 4, 2024
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...
- Publication number 20240088153
- Publication date Mar 14, 2024
- Intel Corporation
- Nicole THOMAS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...
- Publication number 20240047559
- Publication date Feb 8, 2024
- Intel Corporation
- Willy RACHMADY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE SPACER IN STACKED GATE-ALL-AROUND (GAA) DEVICE ARCHITECTURE
- Publication number 20240006499
- Publication date Jan 4, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES
- Publication number 20230420460
- Publication date Dec 28, 2023
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED EMBEDDED SOURCE AND DRAIN CONTACTS
- Publication number 20230420528
- Publication date Dec 28, 2023
- Intel Corporation
- Nitesh Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFUSION CUT STRESSORS FOR STACKED TRANSISTORS
- Publication number 20230420562
- Publication date Dec 28, 2023
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL METAL SILICIDE FOR STACKED TRANSISTOR DEVICES
- Publication number 20230402507
- Publication date Dec 14, 2023
- Intel Corporation
- Rohit Galatage
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE AND DRAIN CONTACTS FORMED USING SACRIFICIAL REGIONS OF SOURC...
- Publication number 20230402513
- Publication date Dec 14, 2023
- Intel Corporation
- Rohit Galatage
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE REMOVAL OF CHANNEL BODIES IN STACKED GATE-ALL-AROUND (GAA...
- Publication number 20230395678
- Publication date Dec 7, 2023
- Intel Corporation
- Munzarin F. Qayyum
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REMOVAL OF UPPER CHANNEL BODIES IN STACKED GATE-ALL-AROUND (GAA) DE...
- Publication number 20230395697
- Publication date Dec 7, 2023
- Intel Corporation
- Nicole K. Thomas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D SOURCE AND DRAIN CONTACTS TUNED FOR VERTICALLY STACKED PMOS AND...
- Publication number 20230395718
- Publication date Dec 7, 2023
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D SOURCE AND DRAIN CONTACTS TUNED FOR PMOS AND NMOS
- Publication number 20230395717
- Publication date Dec 7, 2023
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING AN OXIDE VOLUME WITHIN A FIN
- Publication number 20230377947
- Publication date Nov 23, 2023
- Intel Corporation
- Cheng-Ying HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...
- Publication number 20230369399
- Publication date Nov 16, 2023
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS

Cheng-Chung Huang

Person

Patents Grantslast 30 patents

Gate-to-gate isolation for stacked transistor architecture via sele...

Asymmetric gate structures and contacts for stacked transistors

Transistor with isolation below source and drain

Sideways vias in isolation areas to contact interior layers in stac...

Forksheet transistors with dielectric or conductive spine

Gate-all-around integrated circuit structures having depopulated ch...

Forming an oxide volume within a fin

Thin-film transistors and MIM capacitors in exclusion zones

Stacked source-drain-gate connection and process for forming such

Arrays of double-sided dram cells including capacitors on the front...

Interconnect techniques for electrically connecting source/drain re...

High performance semiconductor oxide material channel regions for NMOS

Epitaxial layer with substantially parallel sides

Leave-behind protective layer having secondary purpose

Stacked forksheet transistors

Three-dimensional integrated circuits (3DICs) including bottom gate...

Sideways vias in isolation areas to contact interior layers in stac...

Non-silicon N-type and P-type stacked transistors for integrated ci...

Ferroelectric gate stack for band-to-band tunneling reduction

Top gate recessed channel CMOS thin film transistor in the back end...

Forksheet transistors with dielectric or conductive spine

Transistor with isolation below source and drain

Stacked source-drain-gate connection and process for forming such

Stacked trigate transistors with dielectric isolation and process f...

Thin film transistor structures with regrown source and drain

Vertical tunneling field-effect transistors

Gate-all-around integrated circuit structures having depopulated ch...

Gate-all-around integrated circuit structures having depopulated ch...

Subfin leakage suppression using fixed charge

Gate-all-around integrated circuit structures having depopulated ch...

Patents Applicationslast 30 patents

CAPPING NANORIBBON FINS IN SUPERLATTICE STRUCTURES DURING FABRICATION

FORKSHEET TRANSISTORS WITH DIELECTRIC OR CONDUCTIVE SPINE

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...

ARRAYS OF DOUBLE-SIDED DRAM CELLS INCLUDING CAPACITORS ON THE FRONT...

STACKED CMOS TRANSISTOR STRUCTURES WITH COMPLEMENTARY CHANNEL MATER...

STACKED FORKSHEET TRANSISTORS

TECHNOLOGIES FOR RIBBON FIELD EFFECT TRANSISTORS WITH VARIABLE FIN...

TECHNOLOGIES FOR RIBBON FIELD EFFECT TRANSISTORS WITH VARIABLE FIN...

NANORIBBON STACKS WITHOUT DIELECTRIC PROTECTION CAPS FOR TOP NANORI...

TRANSISTOR GATE-CHANNEL ARRANGEMENTS WITH MULTIPLE DIPOLE MATERIALS

BACKSIDE CONTACTED SUB-FIN DIODES

SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STAC...

FORKSHEET TRANSISTORS WITH DIELECTRIC OR CONDUCTIVE SPINE

STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH

TOP GATE RECESSED CHANNEL CMOS THIN FILM TRANSISTOR AND METHODS OF...

TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...

GATE SPACER IN STACKED GATE-ALL-AROUND (GAA) DEVICE ARCHITECTURE

LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES

SELF-ALIGNED EMBEDDED SOURCE AND DRAIN CONTACTS

DIFFUSION CUT STRESSORS FOR STACKED TRANSISTORS

DUAL METAL SILICIDE FOR STACKED TRANSISTOR DEVICES

SOURCE AND DRAIN CONTACTS FORMED USING SACRIFICIAL REGIONS OF SOURC...

SELECTIVE REMOVAL OF CHANNEL BODIES IN STACKED GATE-ALL-AROUND (GAA...

REMOVAL OF UPPER CHANNEL BODIES IN STACKED GATE-ALL-AROUND (GAA) DE...

3D SOURCE AND DRAIN CONTACTS TUNED FOR VERTICALLY STACKED PMOS AND...

3D SOURCE AND DRAIN CONTACTS TUNED FOR PMOS AND NMOS

FORMING AN OXIDE VOLUME WITHIN A FIN

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...