Cheng-Gang Kong

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
High speed multiple memory interface I/O cell
- Patent number 8,912,818
- Issue date Dec 16, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Dharmesh Bhakta
- G11 - INFORMATION STORAGE
Information Patent Grant
Feedback programmable data strobe enable architecture for DDR memor...
- Patent number 8,819,354
- Issue date Aug 26, 2014
- LSI Corporation
- Hui-Yin Seto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generic low power strobe based system and method for interfacing me...
- Patent number 8,743,634
- Issue date Jun 3, 2014
- LSI Corporation
- Terence J. Magee
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and computer program for generating grounded shielding wires...
- Patent number 8,516,425
- Issue date Aug 20, 2013
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-linear common coarse delay system and method for delaying data...
- Patent number 8,453,096
- Issue date May 28, 2013
- LSI Corporation
- Terence J. Magee
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed multiple memory interface I/O cell
- Patent number 8,324,927
- Issue date Dec 4, 2012
- LSI Corporation
- Dharmesh Bhakta
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for balancing signal delay skew
- Patent number 8,239,813
- Issue date Aug 7, 2012
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory interface architecture for maximizing access timing margin
- Patent number 8,230,143
- Issue date Jul 24, 2012
- LSI Corporation
- Hui-Yin Seto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal delay skew reduction system
- Patent number 7,996,804
- Issue date Aug 9, 2011
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple memory standard physical layer macro function
- Patent number 7,969,799
- Issue date Jun 28, 2011
- LSI Corporation
- Derrick Sai-Tang Butt
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed multiple memory interface I/O cell
- Patent number 7,876,123
- Issue date Jan 25, 2011
- LSI Corporation
- Dharmesh Bhakta
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable high-speed memory interface subsystem
- Patent number 7,865,661
- Issue date Jan 4, 2011
- LSI Corporation
- Derrick Sai-Tang Butt
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and systems for VT invariant DDR3 SDRAM write leveling
- Patent number 7,839,716
- Issue date Nov 23, 2010
- LSI Corporation
- Cheng-Gang Kong
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for providing swap path voltage and temperature c...
- Patent number 7,571,396
- Issue date Aug 4, 2009
- LSI Logic Corporation
- Thomas Hughes
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for compensating for PVT variation effects on the...
- Patent number 7,454,303
- Issue date Nov 18, 2008
- LSI Logic Corporation
- Terence Magee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable high-speed memory interface subsystem
- Patent number 7,437,500
- Issue date Oct 14, 2008
- LSI Corporation
- Derrick Sai-Tang Butt
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods for improved input/output cells
- Patent number 7,239,170
- Issue date Jul 3, 2007
- LSI Corporation
- Victor Suen
- G11 - INFORMATION STORAGE
Information Patent Grant
Wide-range programmable delay line
- Patent number 7,119,596
- Issue date Oct 10, 2006
- LSI Logic Corporation
- Cheng-Gang Kong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for including the states of nonscannable parts...
- Patent number 5,450,455
- Issue date Sep 12, 1995
- Tandem Computers Incorporated
- Stephen W. Hamilton
- G01 - MEASURING TESTING
Information Patent Grant
Programmable error-checking matrix for digital communication system
- Patent number 5,396,505
- Issue date Mar 7, 1995
- Tandem Computers Incorporated
- Jon C. Freeman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Streamlined instruction processor
- Patent number 4,926,323
- Issue date May 15, 1990
- Advanced Micro Devices, Inc.
- Gigy Baror
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for processing single-cycle branch instruction in a pipeline...
- Patent number 4,777,587
- Issue date Oct 11, 1988
- Advanced Micro Devices, Inc.
- Brian W. Case
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
General-purpose register file optimized for intraprocedural registe...
- Patent number 4,777,588
- Issue date Oct 11, 1988
- Advanced Micro Devices, Inc.
- Brian W. Case
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for performing data references to storage in parallel wit...
- Patent number 4,734,852
- Issue date Mar 29, 1988
- Advanced Micro Devices, Inc.
- William M. Johnson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL
- Publication number 20130049799
- Publication date Feb 28, 2013
- LSI Corporation
- Dharmesh Bhakta
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20120278783
- Publication date Nov 1, 2012
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-LINEAR COMMON COARSE DELAY SYSTEM AND METHOD FOR DELAYING DATA...
- Publication number 20120194248
- Publication date Aug 2, 2012
- LSI CORPORATION
- Terence J. Magee
- G11 - INFORMATION STORAGE
Information Patent Application
GENERIC LOW POWER STROBE BASED SYSTEM AND METHOD FOR INTERFACING ME...
- Publication number 20120195141
- Publication date Aug 2, 2012
- LSI CORPORATION
- Terence J. Magee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20110258587
- Publication date Oct 20, 2011
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL
- Publication number 20110084725
- Publication date Apr 14, 2011
- Dharmesh Bhakta
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND SYSTEMS FOR VT INVARIANT DDR3 SDRAM WRITE LEVELING
- Publication number 20100157700
- Publication date Jun 24, 2010
- Cheng-Gang Kong
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL DELAY SKEW REDUCTION SYSTEM
- Publication number 20090187873
- Publication date Jul 23, 2009
- LSI Corporation
- Andrey Nikitin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple memory standard physical layer macro function
- Publication number 20090091987
- Publication date Apr 9, 2009
- Derrick Sai-Tang Butt
- G11 - INFORMATION STORAGE
Information Patent Application
High speed multiple memory interface I/O cell
- Publication number 20090091349
- Publication date Apr 9, 2009
- Dharmesh Bhakta
- G11 - INFORMATION STORAGE
Information Patent Application
Configurable high-speed memory interface subsystem
- Publication number 20090043955
- Publication date Feb 12, 2009
- Derrick Sai-Tang Butt
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for compensating for PVT variation effects on the...
- Publication number 20080150610
- Publication date Jun 26, 2008
- Terence Magee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for providing swap path voltage and temperature c...
- Publication number 20080068911
- Publication date Mar 20, 2008
- Thomas Hughes
- G11 - INFORMATION STORAGE
Information Patent Application
Configurable high-speed memory interface subsystem
- Publication number 20070033337
- Publication date Feb 8, 2007
- LSI Logic Corporation
- Derrick Sai-Tang Butt
- G11 - INFORMATION STORAGE
Information Patent Application
Feedback programmable data strobe enable architecture for DDR memor...
- Publication number 20060288175
- Publication date Dec 21, 2006
- LSI Logic Corporation
- Hui-Yin Seto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory interface architecture for maximizing access timing margin
- Publication number 20060224847
- Publication date Oct 5, 2006
- LSI Logic Corporation
- Hui-Yin Seto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Wide-range programmable delay line
- Publication number 20060132210
- Publication date Jun 22, 2006
- LSI Logic Corporation
- Cheng-Gang Kong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and methods for improved input/output cells
- Publication number 20050010833
- Publication date Jan 13, 2005
- Victor Suen
- G11 - INFORMATION STORAGE

Cheng-Gang Kong

Person

Patents Grantslast 30 patents

High speed multiple memory interface I/O cell

Feedback programmable data strobe enable architecture for DDR memor...

Generic low power strobe based system and method for interfacing me...

Method and computer program for generating grounded shielding wires...

Non-linear common coarse delay system and method for delaying data...

High speed multiple memory interface I/O cell

Method and apparatus for balancing signal delay skew

Memory interface architecture for maximizing access timing margin

Signal delay skew reduction system

Multiple memory standard physical layer macro function

High speed multiple memory interface I/O cell

Configurable high-speed memory interface subsystem

Apparatus and systems for VT invariant DDR3 SDRAM write leveling

System and method for providing swap path voltage and temperature c...

System and method for compensating for PVT variation effects on the...

Configurable high-speed memory interface subsystem

Apparatus and methods for improved input/output cells

Wide-range programmable delay line

Method and apparatus for including the states of nonscannable parts...

Programmable error-checking matrix for digital communication system

Streamlined instruction processor

System for processing single-cycle branch instruction in a pipeline...

General-purpose register file optimized for intraprocedural registe...

Mechanism for performing data references to storage in parallel wit...

Patents Applicationslast 30 patents

HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL

SIGNAL DELAY SKEW REDUCTION SYSTEM

NON-LINEAR COMMON COARSE DELAY SYSTEM AND METHOD FOR DELAYING DATA...

GENERIC LOW POWER STROBE BASED SYSTEM AND METHOD FOR INTERFACING ME...

SIGNAL DELAY SKEW REDUCTION SYSTEM

HIGH SPEED MULTIPLE MEMORY INTERFACE I/O CELL

APPARATUS AND SYSTEMS FOR VT INVARIANT DDR3 SDRAM WRITE LEVELING

SIGNAL DELAY SKEW REDUCTION SYSTEM

Multiple memory standard physical layer macro function

High speed multiple memory interface I/O cell

Configurable high-speed memory interface subsystem

System and method for compensating for PVT variation effects on the...

System and method for providing swap path voltage and temperature c...

Configurable high-speed memory interface subsystem

Feedback programmable data strobe enable architecture for DDR memor...

Memory interface architecture for maximizing access timing margin

Wide-range programmable delay line

Apparatus and methods for improved input/output cells