Chester T. Dziobkowski

Person

Hopewell Junction, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for preventing backside defects in dielectric layers formed...
- Patent number 7,910,484
- Issue date Mar 22, 2011
- International Business Machines Corporation
- Chester T. Dziobkowski
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Structure to improve adhesion between top CVD low-K dielectric and...
- Patent number 7,820,559
- Issue date Oct 26, 2010
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of fully silicided metal gate using dual self-aligned sil...
- Patent number 7,785,999
- Issue date Aug 31, 2010
- International Business Machines Corporation
- Cyril Cabral, Jr.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure to improve adhesion between top CVD low-k dielectric and...
- Patent number 7,402,532
- Issue date Jul 22, 2008
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of fully silicided metal gate using dual self-aligned sil...
- Patent number 7,271,455
- Issue date Sep 18, 2007
- International Business Machines Corporation
- Cyril Cabral, Jr.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming low resistance and reliable via in inter-level di...
- Patent number 7,223,691
- Issue date May 29, 2007
- International Business Machines Corporation
- Cyril Cabral, Jr.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming self-aligned dual fully silicided gates in CMOS...
- Patent number 7,122,472
- Issue date Oct 17, 2006
- International Business Machines Corporation
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming self-aligned dual salicide in CMOS technologies
- Patent number 7,112,481
- Issue date Sep 26, 2006
- International Business Machines Corporation
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure to improve adhesion between top CVD low-k dielectric and...
- Patent number 7,102,232
- Issue date Sep 5, 2006
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming self-aligned dual salicide in CMOS technologies
- Patent number 7,067,368
- Issue date Jun 27, 2006
- International Business Machines Corporation
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming self-aligned dual salicide in CMOS technologies
- Patent number 7,064,025
- Issue date Jun 20, 2006
- International Business Machines Corporation
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low Cu percentages for reducing shorts in AlCu lines
- Patent number 6,960,306
- Issue date Nov 1, 2005
- Infineon Technologies AG
- Roy C. Iggulden
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Salicide formation method
- Patent number 6,916,729
- Issue date Jul 12, 2005
- Infineon Technologies AG
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Laminated diffusion barrier
- Patent number 6,726,996
- Issue date Apr 27, 2004
- International Business Machines Corporation
- Edward Paul Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and materials for depositing films on semiconductor substrates
- Patent number 6,500,772
- Issue date Dec 31, 2002
- International Business Machines Corporation
- Ashima B. Chakravarti
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Charged particle beam apparatus having anticontamination means
- Patent number 6,046,457
- Issue date Apr 4, 2000
- International Business Machines Corporation
- Carl E. Bohnenkamp
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR PREVENTING BACKSIDE DEFECTS IN DIELECTRIC LAYERS FORMED...
- Publication number 20090181544
- Publication date Jul 16, 2009
- Chester T. Dziobkowski
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
STRUCTURE TO IMPROVE ADHESION BETWEEN TOP CVD LOW-K DIELECTRIC AND...
- Publication number 20080254643
- Publication date Oct 16, 2008
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF FULLY SILICIDED METAL GATE USING DUAL SELF-ALIGNED SIL...
- Publication number 20080026551
- Publication date Jan 31, 2008
- International Business Machines Corporation
- Cyril Cabral
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure to improve adhesion between top CVD low-k dielectric and...
- Publication number 20070148958
- Publication date Jun 28, 2007
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming self-aligned dual salicide in CMOS technologies
- Publication number 20060121664
- Publication date Jun 8, 2006
- International Business Machines Corporation
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING SELF-ALIGNED DUAL FULLY SILICIDED GATES IN CMOS...
- Publication number 20060121663
- Publication date Jun 8, 2006
- International Business Machines Corporation
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES
- Publication number 20060121662
- Publication date Jun 8, 2006
- International Business Machines Corporation
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES
- Publication number 20060121665
- Publication date Jun 8, 2006
- International Business Machines Corporation
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming low resistance and reliable via in inter-level di...
- Publication number 20060084256
- Publication date Apr 20, 2006
- International Business Machines Corporation
- Cyril Cabral
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Formation of fully silicided metal gate using dual self-aligned sil...
- Publication number 20060022280
- Publication date Feb 2, 2006
- International Business Machines Corporation
- Cyril Cabral
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure to improve adhesion between top CVD low-k dielectiric and...
- Publication number 20050230831
- Publication date Oct 20, 2005
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Salicide formation method
- Publication number 20040203229
- Publication date Oct 14, 2004
- Sunfei Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low Cu percentages for reducing shorts in AlCu lines
- Publication number 20040020891
- Publication date Feb 5, 2004
- Infineon Technologies North America Corp.
- Roy C. Iggulden
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Laminated diffusion barrier
- Publication number 20020172811
- Publication date Nov 21, 2002
- International Business Machines Corporation
- Edward Paul Barth
- B32 - LAYERED PRODUCTS
Information Patent Application
Methods and materials for depositing films on semiconductor substrates
- Publication number 20020090835
- Publication date Jul 11, 2002
- Ashima B. Chakravarti
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Chester T. Dziobkowski

Person

Patents Grantslast 30 patents

Method for preventing backside defects in dielectric layers formed...

Structure to improve adhesion between top CVD low-K dielectric and...

Formation of fully silicided metal gate using dual self-aligned sil...

Structure to improve adhesion between top CVD low-k dielectric and...

Formation of fully silicided metal gate using dual self-aligned sil...

Method of forming low resistance and reliable via in inter-level di...

Method for forming self-aligned dual fully silicided gates in CMOS...

Method for forming self-aligned dual salicide in CMOS technologies

Structure to improve adhesion between top CVD low-k dielectric and...

Method for forming self-aligned dual salicide in CMOS technologies

Method for forming self-aligned dual salicide in CMOS technologies

Low Cu percentages for reducing shorts in AlCu lines

Salicide formation method

Laminated diffusion barrier

Methods and materials for depositing films on semiconductor substrates

Charged particle beam apparatus having anticontamination means

Patents Applicationslast 30 patents

METHOD FOR PREVENTING BACKSIDE DEFECTS IN DIELECTRIC LAYERS FORMED...

STRUCTURE TO IMPROVE ADHESION BETWEEN TOP CVD LOW-K DIELECTRIC AND...

FORMATION OF FULLY SILICIDED METAL GATE USING DUAL SELF-ALIGNED SIL...

Structure to improve adhesion between top CVD low-k dielectric and...

Method for forming self-aligned dual salicide in CMOS technologies

METHOD FOR FORMING SELF-ALIGNED DUAL FULLY SILICIDED GATES IN CMOS...

METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES

METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES

Method of forming low resistance and reliable via in inter-level di...

Formation of fully silicided metal gate using dual self-aligned sil...

Structure to improve adhesion between top CVD low-k dielectiric and...

Salicide formation method

Low Cu percentages for reducing shorts in AlCu lines

Laminated diffusion barrier

Methods and materials for depositing films on semiconductor substrates