Chethan Swamynathan

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Bangalore, IN

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Patents Grantslast 30 patents

Information Patent Grant
Integrated device comprising device level cells with variable sizes...
- Patent number 10,141,297
- Issue date Nov 27, 2018
- QUALCOMM Incorporated
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and layout techniques for flop tray area and power otimization
- Patent number 9,024,658
- Issue date May 5, 2015
- QUALCOMM Incorporated
- Jay Madhukar Shah
- G01 - MEASURING TESTING
Information Patent Grant
Standard cell architecture using double poly patterning for multi V...
- Patent number 8,610,176
- Issue date Dec 17, 2013
- QUALCOMM Incorporated
- Prayag B. Patel
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
FINE GRAIN POWER GATING
- Publication number 20240322819
- Publication date Sep 26, 2024
- QUALCOMM Incorporated
- Giby SAMSON
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUIT AND LAYOUT TECHNIQUES FOR FLOP TRAY AREA AND POWER OTIMIZATION
- Publication number 20140359385
- Publication date Dec 4, 2014
- QUALCOMM Incorporated
- Jay Madhukar Shah
- G01 - MEASURING TESTING
Information Patent Application
AREA EFFICIENT GRIDDED POLYSILICON LAYOUTS
- Publication number 20130032885
- Publication date Feb 7, 2013
- QUALCOMM Incorporated
- Chethan Swamynathan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Standard Cell Architecture Using Double Poly Patterning for Multi V...
- Publication number 20120180016
- Publication date Jul 12, 2012
- QUALCOMM Incorporated
- PR Chidambaram
- H01 - BASIC ELECTRIC ELEMENTS