Chi-San Wei

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Hsin-Chu, TW

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Patents Grantslast 30 patents

Information Patent Grant
Fully isolated high-voltage MOS device
- Patent number 8,236,642
- Issue date Aug 7, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-San Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fully isolated high-voltage MOS device
- Patent number 7,843,002
- Issue date Nov 30, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-San Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Robust ESD LDMOS device
- Patent number 7,781,834
- Issue date Aug 24, 2010
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-San Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Alignment strategy for asymmetrical alignment marks
- Patent number 6,074,950
- Issue date Jun 13, 2000
- United Integrated Circuits Corp.
- Chi-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for aligning shallow trench isolation
- Patent number 5,950,093
- Issue date Sep 7, 1999
- Chi-Hung Wei
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Fully Isolated High-Voltage MOS Device
- Publication number 20110039387
- Publication date Feb 17, 2011
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-San Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Robust ESD LDMOS Device
- Publication number 20090008710
- Publication date Jan 8, 2009
- Chi-San Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fully Isolated High-Voltage MOS Device
- Publication number 20090008711
- Publication date Jan 8, 2009
- Chi-San Wei
- H01 - BASIC ELECTRIC ELEMENTS