Chi-Wei HU

Person

Taoyuan County, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method and layout of an integrated circuit
- Patent number 11,714,947
- Issue date Aug 1, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd
- Mahantesh Hanchinal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and layout of an integrated circuit
- Patent number 11,341,308
- Issue date May 24, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd
- Mahantesh Hanchinal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and layout of an integrated circuit
- Patent number 10,936,780
- Issue date Mar 2, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd
- Mahantesh Hanchinal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and layout of an integrated circuit
- Patent number 10,402,529
- Issue date Sep 3, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd
- Mahantesh Hanchinal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for multi-patterning
- Patent number 10,268,791
- Issue date Apr 23, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd
- Yen-Hung Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system and computer program product for generating layout f...
- Patent number 9,659,133
- Issue date May 23, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yen-Hung Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tier based layer promotion and demotion
- Patent number 9,436,793
- Issue date Sep 6, 2016
- Taiwan Semiconductor Manufacturing Company Limited
- Yen-Hung Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor arrangement formation
- Patent number 9,405,880
- Issue date Aug 2, 2016
- Taiwan Semiconductor Manufacturing Company Limited
- Yen-Hung Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for placing decoupling capacitors
- Patent number 8,739,097
- Issue date May 27, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Wei Hu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for on-chip sampling of dynamic IR voltage drop
- Patent number 8,614,571
- Issue date Dec 24, 2013
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Nan-Hsin Tseng
- G01 - MEASURING TESTING
Information Patent Grant
System and method for reducing processor power consumption
- Patent number 8,347,132
- Issue date Jan 1, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Lee-Chung Lu
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System and method for characterizing process variations
- Patent number 8,258,883
- Issue date Sep 4, 2012
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Wei Chen
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT
- Publication number 20220284165
- Publication date Sep 8, 2022
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mahantesh HANCHINAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT
- Publication number 20210173996
- Publication date Jun 10, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mahantesh HANCHINAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT
- Publication number 20190392108
- Publication date Dec 26, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mahantesh HANCHINAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT
- Publication number 20180144082
- Publication date May 24, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mahantesh HANCHINAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR MULTI-PATTERNING
- Publication number 20170169154
- Publication date Jun 15, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yen-Hung LIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR ARRANGEMENT FORMATION
- Publication number 20150331990
- Publication date Nov 19, 2015
- Taiwan Semiconductor Manufacturing Company Limited
- Yen-Hung Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIER BASED LAYER PROMOTION AND DEMOTION
- Publication number 20150213178
- Publication date Jul 30, 2015
- Taiwan Semiconductor Manufacturing Company Limited
- Yen-Hung Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING LAYOUT F...
- Publication number 20150113493
- Publication date Apr 23, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yen-Hung LIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR PLACING DECOUPLING CAPACITORS
- Publication number 20140082575
- Publication date Mar 20, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Wei Hu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR ON-CHIP SAMPLING OF DYNAMIC IR VOLTAGE DROP
- Publication number 20130127441
- Publication date May 23, 2013
- Taiwan Semiconductor Manufacturing Co., LTD
- Nan-Hsin TSENG
- G01 - MEASURING TESTING
Information Patent Application
System and Method for Characterizing Process Variations
- Publication number 20100176890
- Publication date Jul 15, 2010
- Yi-Wei Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and Method for Reducing Processor Power Consumption
- Publication number 20100174933
- Publication date Jul 8, 2010
- Lee-Chung Lu
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Method and layout of an integrated circuit

Method and layout of an integrated circuit

Method and layout of an integrated circuit

Method and layout of an integrated circuit

System and method for multi-patterning

Method, system and computer program product for generating layout f...

Tier based layer promotion and demotion

Semiconductor arrangement formation

Method for placing decoupling capacitors

Apparatus and method for on-chip sampling of dynamic IR voltage drop

System and method for reducing processor power consumption

System and method for characterizing process variations

Patents Applicationslast 30 patents

METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT

METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT

METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT

METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT

SYSTEM AND METHOD FOR MULTI-PATTERNING

SEMICONDUCTOR ARRANGEMENT FORMATION

TIER BASED LAYER PROMOTION AND DEMOTION

METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERATING LAYOUT F...

METHOD FOR PLACING DECOUPLING CAPACITORS

APPARATUS AND METHOD FOR ON-CHIP SAMPLING OF DYNAMIC IR VOLTAGE DROP

System and Method for Characterizing Process Variations

System and Method for Reducing Processor Power Consumption