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Chi-Yeu Chao
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Beaverton, OR, US
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Patents Grants
last 30 patents
Information
Patent Grant
Phase-locked loop having dynamically adjustable up/down pulse widths
Patent number
7,404,099
Issue date
Jul 22, 2008
Intel Corporation
Mingwei Huang
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Input circuit with switched reference signals
Patent number
6,781,428
Issue date
Aug 24, 2004
Intel Corporation
Chi-Yeu Chao
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Clocking an I/O buffer, having a selectable phase difference from t...
Patent number
6,748,549
Issue date
Jun 8, 2004
Intel Corporation
Chi-Yeu Chao
G01 - MEASURING TESTING
Information
Patent Grant
I/O device testing method and apparatus
Patent number
6,671,847
Issue date
Dec 30, 2003
Intel Corporation
Chi-Yeu Chao
G11 - INFORMATION STORAGE
Information
Patent Grant
Input circuit with non-delayed time blanking
Patent number
6,552,570
Issue date
Apr 22, 2003
Intel Corporation
Gregory F. Taylor
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Self-configurable clock input buffer compatible with high-voltage s...
Patent number
6,407,591
Issue date
Jun 18, 2002
Intel Corporation
Keng L. Wong
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Clocked sense amplifier flip flop with keepers to prevent floating...
Patent number
6,396,309
Issue date
May 28, 2002
Intel Corporation
Cangsang Zhao
G11 - INFORMATION STORAGE
Patents Applications
last 30 patents
Information
Patent Application
Phase-locked loop having dynamically adjustable up/down pulse widths
Publication number
20060034403
Publication date
Feb 16, 2006
Mingwei Huang
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
Input circuit with non-delayed time blanking
Publication number
20030001617
Publication date
Jan 2, 2003
Gregory F. Taylor
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Application
Input circuit with switched reference signals
Publication number
20030001644
Publication date
Jan 2, 2003
Chi-Yeu Chao
H03 - BASIC ELECTRONIC CIRCUITRY