Chien-Chu Kuo

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Circuit design system and method of generating hierarchical block-l...
- Patent number 8,977,994
- Issue date Mar 10, 2015
- Cadence Design Systems, Inc.
- Oleg Levitsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of generating hierarchical block-level timing con...
- Patent number 7,926,011
- Issue date Apr 12, 2011
- Cadence Design Systems, Inc.
- Oleg Levitsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for clock tree synthesis of an integrated circuit
- Patent number 7,467,367
- Issue date Dec 16, 2008
- Cadence Design Systems, Inc.
- Hung-Chun Li
- G06 - COMPUTING CALCULATING COUNTING