Chih Chin Liao

Person

Yuanlin Town, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Substrate bonding pad having a multi-surface trace interface
- Patent number 11,569,155
- Issue date Jan 31, 2023
- Western Digital Technologies, Inc.
- Chih-Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Side contact pads for high-speed memory card
- Patent number 11,425,817
- Issue date Aug 23, 2022
- Western Digital Technologies, Inc.
- Shineng Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Printed circuit board trace for galvanic effect reduction
- Patent number 11,234,327
- Issue date Jan 25, 2022
- Western Digital Technologies, Inc.
- Songtao Lu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor device including control switches to reduce pin capac...
- Patent number 11,177,239
- Issue date Nov 16, 2021
- SanDisk Information Technology (Shanghai) Co., Ltd.
- Shineng Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including dummy pull-down wire bonds
- Patent number 11,031,372
- Issue date Jun 8, 2021
- Western Digital Technologies, Inc.
- Han-Shiao Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heterogeneous fan-out structures for memory devices
- Patent number 10,607,955
- Issue date Mar 31, 2020
- SanDisk Semiconductor (Shanghai) Co. Ltd.
- Chin-Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire bonded wide I/O semiconductor device
- Patent number 10,249,592
- Issue date Apr 2, 2019
- SanDisk Technologies LLC
- Michael Mostovoy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including optional pad interconnect
- Patent number 10,249,587
- Issue date Apr 2, 2019
- Western Digital Technologies, Inc.
- Han-Shiao Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including support pillars on solder mask
- Patent number 10,177,128
- Issue date Jan 8, 2019
- SanDisk Technologies LLC
- Chih Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Printed circuit board with coextensive electrical connectors and co...
- Patent number 10,051,733
- Issue date Aug 14, 2018
- SanDisk Technologies Inc.
- Chih-Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wire bonded wide I/O semiconductor device
- Patent number 9,899,347
- Issue date Feb 20, 2018
- SanDisk Technologies LLC
- Michael Mostovoy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Rigid wave pattern design on chip carrier substrate and printed cir...
- Patent number 9,230,919
- Issue date Jan 5, 2016
- SanDisk Technologies Inc.
- Chin-Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hidden plating traces
- Patent number 9,209,159
- Issue date Dec 8, 2015
- SanDisk Technologies Inc.
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Printed circuit board with coextensive electrical connectors and co...
- Patent number 9,006,912
- Issue date Apr 14, 2015
- SanDisk Technologies Inc.
- Chih-Chin Liao
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Rigid wave pattern design on chip carrier substrate and printed cir...
- Patent number 8,878,368
- Issue date Nov 4, 2014
- SanDisk Technologies Inc.
- Chin-Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density three dimensional semiconductor die package
- Patent number 8,653,653
- Issue date Feb 18, 2014
- SanDisk Technologies Inc.
- Cheeman Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Two-sided substrate lead connection for minimizing kerf width on a...
- Patent number 8,637,972
- Issue date Jan 28, 2014
- SanDisk Technologies Inc.
- Chih-Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Radiation-shielded semiconductor device
- Patent number 8,637,963
- Issue date Jan 28, 2014
- SanDisk Technologies Inc.
- Suresh Kumar Upadhyayula
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Corrugated die edge for stacked die semiconductor package
- Patent number 8,502,375
- Issue date Aug 6, 2013
- SanDisk Technologies Inc.
- Chih-Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Rigid wave pattern design on chip carrier substrate and printed cir...
- Patent number 8,487,441
- Issue date Jul 16, 2013
- SanDisk Technologies Inc.
- Chin-Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating stacked semiconductor package with localized...
- Patent number 8,470,640
- Issue date Jun 25, 2013
- SanDisk Technologies Inc.
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate panel with plating bar structured to allow minimum kerf w...
- Patent number 8,461,675
- Issue date Jun 11, 2013
- SanDisk Technologies Inc.
- Hem Takiar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor device with die stack arrangement including staggered...
- Patent number 8,415,808
- Issue date Apr 9, 2013
- SanDisk Technologies Inc.
- Chih-Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked semiconductor package with localized cavities for wire bonding
- Patent number 8,294,251
- Issue date Oct 23, 2012
- SanDisk Technologies Inc.
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Printed circuit board with coextensive electrical connectors and co...
- Patent number 8,217,522
- Issue date Jul 10, 2012
- SanDisk Technologies Inc.
- Chih-Chin Liao
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Hidden plating traces
- Patent number 8,129,272
- Issue date Mar 6, 2012
- SanDisk Technologies Inc.
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die package with asymmetric leadframe connection
- Patent number 8,097,495
- Issue date Jan 17, 2012
- SanDisk Technologies Inc.
- Ming Hsun Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked, interconnected semiconductor package
- Patent number 8,053,880
- Issue date Nov 8, 2011
- SanDisk Technologies, Inc
- Cheeman Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Padless substrate for surface mounted components
- Patent number 7,967,184
- Issue date Jun 28, 2011
- SanDisk Corporation
- Chih-Chin Liao
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor package having through holes for molding back side of...
- Patent number 7,952,179
- Issue date May 31, 2011
- SanDisk Corporation
- Chin-Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Substrate Bonding Pad Having a Multi-Surface Trace Interface
- Publication number 20220399258
- Publication date Dec 15, 2022
- Western Digital Technologies, Inc.
- Chih-Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIDE CONTACT PADS FOR HIGH-SPEED MEMORY CARD
- Publication number 20210400811
- Publication date Dec 23, 2021
- Western Digital Technologies, Inc.
- SHINENG MA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING DUMMY PULL-DOWN WIRE BONDS
- Publication number 20190341366
- Publication date Nov 7, 2019
- Western Digital Technologies, Inc.
- Han-Shiao Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING CONTROL SWITCHES TO REDUCE PIN CAPAC...
- Publication number 20190006320
- Publication date Jan 3, 2019
- SANDISK INFORMATION TECHNOLOGY (SHANGHAI) CO., LTD.
- Shineng Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HETEROGENEOUS FAN-OUT STRUCTURES FOR MEMORY DEVICES
- Publication number 20180366429
- Publication date Dec 20, 2018
- SunDisk Semiconductro (Shanghai) Co. Ltd.
- Chin-Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WIRE BONDED WIDE I/O SEMICONDUCTOR DEVICE
- Publication number 20180174996
- Publication date Jun 21, 2018
- SanDisk Technologies LLC
- Michael Mostovoy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING SUPPORT PILLARS ON SOLDER MASK
- Publication number 20160293560
- Publication date Oct 6, 2016
- SANDISK TECHNOLOGIES INC.
- Chih Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PRINTED CIRCUIT BOARD WITH COEXTENSIVE ELECTRICAL CONNECTORS AND CO...
- Publication number 20150223335
- Publication date Aug 6, 2015
- SANDISK TECHNOLOGIES INC.
- Chih-Chin Liao
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
RIGID WAVE PATTERN DESIGN ON CHIP CARRIER SUBSTRATE AND PRINTED CIR...
- Publication number 20150054177
- Publication date Feb 26, 2015
- SANDISK TECHNOLOGIES INC.
- Chin-Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RIGID WAVE PATTERN DESIGN ON CHIP CARRIER SUBSTRATE AND PRINTED CIR...
- Publication number 20130299959
- Publication date Nov 14, 2013
- Chin-Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH DIE STACK ARRANGEMENT INCLUDING STAGGERED...
- Publication number 20130207280
- Publication date Aug 15, 2013
- SANDISK TECHNOLOGIES INC.
- Chih-Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RADIATION-SHIELDED SEMICONDUCTOR DEVICE
- Publication number 20130087895
- Publication date Apr 11, 2013
- Suresh Kumar Upadhyayula
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP-ON-PACKAGE STRUCTURE FOR MULTIPLE DIE STACKS
- Publication number 20130015589
- Publication date Jan 17, 2013
- Chih-Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Printed Circuit Board With Coextensive Electrical Connectors And Co...
- Publication number 20120273968
- Publication date Nov 1, 2012
- Chih-Chin Liao
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
GLOB TOP SEMICONDUCTOR PACKAGE
- Publication number 20120193802
- Publication date Aug 2, 2012
- Chin-Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIDDEN PLATING TRACES
- Publication number 20120164828
- Publication date Jun 28, 2012
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH DIE STACK ARRANGEMENT INCLUDING STAGGERED...
- Publication number 20120025396
- Publication date Feb 2, 2012
- Chih-Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CORRUGATED DIE EDGE FOR STACKED DIE SEMICONDUCTOR PACKAGE
- Publication number 20110316164
- Publication date Dec 29, 2011
- Chih-Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Printed Circuit Board With Coextensive Electrical Connectors And Co...
- Publication number 20100252315
- Publication date Oct 7, 2010
- Chih-Chin Liao
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
HIGH DENSITY THREE DIMENSIONAL SEMICONDUCTOR DIE PACKAGE
- Publication number 20100102440
- Publication date Apr 29, 2010
- Cheemen Yu
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF STACKING AND INTERCONNECTING SEMICONDUCTOR PACKAGES VIA E...
- Publication number 20100055835
- Publication date Mar 4, 2010
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF STACKING AND INTERCONNECTING SEMICONDUCTOR PACKAGES VIA E...
- Publication number 20100055836
- Publication date Mar 4, 2010
- Cheeman Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SEMICONDUCTOR PACKAGE WITH LOCALIZED CAVITIES FOR WIRE BONDING
- Publication number 20090321950
- Publication date Dec 31, 2009
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING STACKED SEMICONDUCTOR PACKAGE WITH LOCALIZED...
- Publication number 20090325342
- Publication date Dec 31, 2009
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIDDEN PLATING TRACES
- Publication number 20090263969
- Publication date Oct 22, 2009
- Hem Takiar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED, INTERCONNECTED SEMICONDUCTOR PACKAGE
- Publication number 20090256249
- Publication date Oct 15, 2009
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A SEMICONDUCTOR DIE HAVING A SLOPED EDGE FOR RECE...
- Publication number 20090065902
- Publication date Mar 12, 2009
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES FOR MOLDING BACK SIDE OF...
- Publication number 20090001552
- Publication date Jan 1, 2009
- Chin-Tien Chiu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES...
- Publication number 20090004785
- Publication date Jan 1, 2009
- Chin-Tien Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-SIDED SUBSTRATE LEAD CONNECTION FOR MINIMIZING KERF WIDTH ON A...
- Publication number 20080303166
- Publication date Dec 11, 2008
- Chih-Chin Liao
- H01 - BASIC ELECTRIC ELEMENTS

Chih Chin Liao

Person

Patents Grantslast 30 patents

Substrate bonding pad having a multi-surface trace interface

Side contact pads for high-speed memory card

Printed circuit board trace for galvanic effect reduction

Semiconductor device including control switches to reduce pin capac...

Semiconductor device including dummy pull-down wire bonds

Heterogeneous fan-out structures for memory devices

Wire bonded wide I/O semiconductor device

Semiconductor device including optional pad interconnect

Semiconductor device including support pillars on solder mask

Printed circuit board with coextensive electrical connectors and co...

Wire bonded wide I/O semiconductor device

Rigid wave pattern design on chip carrier substrate and printed cir...

Hidden plating traces

Printed circuit board with coextensive electrical connectors and co...

Rigid wave pattern design on chip carrier substrate and printed cir...

High density three dimensional semiconductor die package

Two-sided substrate lead connection for minimizing kerf width on a...

Radiation-shielded semiconductor device

Corrugated die edge for stacked die semiconductor package

Rigid wave pattern design on chip carrier substrate and printed cir...

Method of fabricating stacked semiconductor package with localized...

Substrate panel with plating bar structured to allow minimum kerf w...

Semiconductor device with die stack arrangement including staggered...

Stacked semiconductor package with localized cavities for wire bonding

Printed circuit board with coextensive electrical connectors and co...

Hidden plating traces

Die package with asymmetric leadframe connection

Stacked, interconnected semiconductor package

Padless substrate for surface mounted components

Semiconductor package having through holes for molding back side of...

Patents Applicationslast 30 patents

Substrate Bonding Pad Having a Multi-Surface Trace Interface

SIDE CONTACT PADS FOR HIGH-SPEED MEMORY CARD

SEMICONDUCTOR DEVICE INCLUDING DUMMY PULL-DOWN WIRE BONDS

SEMICONDUCTOR DEVICE INCLUDING CONTROL SWITCHES TO REDUCE PIN CAPAC...

HETEROGENEOUS FAN-OUT STRUCTURES FOR MEMORY DEVICES

WIRE BONDED WIDE I/O SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE INCLUDING SUPPORT PILLARS ON SOLDER MASK

PRINTED CIRCUIT BOARD WITH COEXTENSIVE ELECTRICAL CONNECTORS AND CO...

RIGID WAVE PATTERN DESIGN ON CHIP CARRIER SUBSTRATE AND PRINTED CIR...

RIGID WAVE PATTERN DESIGN ON CHIP CARRIER SUBSTRATE AND PRINTED CIR...

SEMICONDUCTOR DEVICE WITH DIE STACK ARRANGEMENT INCLUDING STAGGERED...

RADIATION-SHIELDED SEMICONDUCTOR DEVICE

CHIP-ON-PACKAGE STRUCTURE FOR MULTIPLE DIE STACKS

Printed Circuit Board With Coextensive Electrical Connectors And Co...

GLOB TOP SEMICONDUCTOR PACKAGE

HIDDEN PLATING TRACES

SEMICONDUCTOR DEVICE WITH DIE STACK ARRANGEMENT INCLUDING STAGGERED...

CORRUGATED DIE EDGE FOR STACKED DIE SEMICONDUCTOR PACKAGE

Printed Circuit Board With Coextensive Electrical Connectors And Co...

HIGH DENSITY THREE DIMENSIONAL SEMICONDUCTOR DIE PACKAGE

METHOD OF STACKING AND INTERCONNECTING SEMICONDUCTOR PACKAGES VIA E...

METHOD OF STACKING AND INTERCONNECTING SEMICONDUCTOR PACKAGES VIA E...

STACKED SEMICONDUCTOR PACKAGE WITH LOCALIZED CAVITIES FOR WIRE BONDING

METHOD OF FABRICATING STACKED SEMICONDUCTOR PACKAGE WITH LOCALIZED...

HIDDEN PLATING TRACES

STACKED, INTERCONNECTED SEMICONDUCTOR PACKAGE

METHOD OF FORMING A SEMICONDUCTOR DIE HAVING A SLOPED EDGE FOR RECE...

SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES FOR MOLDING BACK SIDE OF...

METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES...

TWO-SIDED SUBSTRATE LEAD CONNECTION FOR MINIMIZING KERF WIDTH ON A...