Chihhung Liao

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable logic device with design for test functionality
- Patent number 12,217,811
- Issue date Feb 4, 2025
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration latch for programmable logic device
- Patent number 12,149,244
- Issue date Nov 19, 2024
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Grant
Area-efficient configuration latch for programmable logic device
- Patent number 11,935,618
- Issue date Mar 19, 2024
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration latch for programmable logic device
- Patent number 11,848,671
- Issue date Dec 19, 2023
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device with design for test functionality
- Patent number 11,848,066
- Issue date Dec 19, 2023
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Grant
Sectional configuration for programmable logic devices
- Patent number 11,652,486
- Issue date May 16, 2023
- QuickLogic Corporation
- Ket Chong Yap
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
State sensing system for eFuse memory
- Patent number 8,780,604
- Issue date Jul 15, 2014
- International Business Machines Corporation
- Chihhung Liao
- G11 - INFORMATION STORAGE
Information Patent Grant
Maskable dynamic logic
- Patent number 7,215,154
- Issue date May 8, 2007
- International Business Machines Corporation
- Derick Gardner Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE
- Publication number 20240171178
- Publication date May 23, 2024
- QuickLogic Corporation
- Ket Chong YAP
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY
- Publication number 20240170087
- Publication date May 23, 2024
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Application
SECTIONAL CONFIGURATION FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20230353156
- Publication date Nov 2, 2023
- QuickLogic Corporation
- Ket Chong YAP
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
AREA-EFFICIENT CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE
- Publication number 20230343372
- Publication date Oct 26, 2023
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY
- Publication number 20230317192
- Publication date Oct 5, 2023
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE
- Publication number 20230299773
- Publication date Sep 21, 2023
- QuickLogic Corporation
- Ket Chong YAP
- G11 - INFORMATION STORAGE
Information Patent Application
STATE SENSING SYSTEM FOR EFUSE MEMORY
- Publication number 20140003120
- Publication date Jan 2, 2014
- International Business Machines Corporation
- Chihhung Liao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Maskable dynamic logic
- Publication number 20070018690
- Publication date Jan 25, 2007
- International Business Machines Corporation
- Derick Gardner Behrends
- H03 - BASIC ELECTRONIC CIRCUITRY

Chihhung Liao

Person

Patents Grantslast 30 patents

Programmable logic device with design for test functionality

Configuration latch for programmable logic device

Area-efficient configuration latch for programmable logic device

Configuration latch for programmable logic device

Programmable logic device with design for test functionality

Sectional configuration for programmable logic devices

State sensing system for eFuse memory

Maskable dynamic logic

Patents Applicationslast 30 patents

CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE

PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY

SECTIONAL CONFIGURATION FOR PROGRAMMABLE LOGIC DEVICES

AREA-EFFICIENT CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE

PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY

CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE

STATE SENSING SYSTEM FOR EFUSE MEMORY

Maskable dynamic logic