Ching-Te Kent Chuang

Person

South Salem, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for varying a supply voltage or reference vol...
- Patent number 9,076,509
- Issue date Jul 7, 2015
- International Business Machines Corporation
- Ching-Te Kent Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Enhanced static random access memory stability using asymmetric acc...
- Patent number 8,526,219
- Issue date Sep 3, 2013
- International Business Machines Corporation
- Aditya Bansal
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure for high density stable static random access memory
- Patent number 8,405,129
- Issue date Mar 26, 2013
- International Business Machines Corporation
- Ching-Te K. Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density stable static random access memory
- Patent number 8,217,427
- Issue date Jul 10, 2012
- International Business Machines Corporation
- Ching-Te K. Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced static random access memory stability using asymmetric acc...
- Patent number 8,139,400
- Issue date Mar 20, 2012
- International Business Machines Corporation
- Aditya Bansal
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for characterizing device variation in electronic memory ci...
- Patent number 8,086,917
- Issue date Dec 27, 2011
- International Business Machines Corporation
- Ching-Te K. Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
High-density logic techniques with reduced-stack multi-gate field e...
- Patent number 8,030,971
- Issue date Oct 4, 2011
- International Business Machines Corporation
- Meng-Hsueh Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-density low-power data retention power gating with double-gate...
- Patent number 7,956,669
- Issue date Jun 7, 2011
- International Business Machines Corporation
- Ching-Te K. Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for varying a supply voltage or reference vol...
- Patent number 7,952,422
- Issue date May 31, 2011
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Asymmetrical memory cells and memories using the cells
- Patent number 7,903,450
- Issue date Mar 8, 2011
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual gate transistor keeper dynamic logic
- Patent number 7,876,131
- Issue date Jan 25, 2011
- International Business Machines Corporation
- Ching-Te Chuang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Independent-gate controlled asymmetrical memory cell and memory usi...
- Patent number 7,787,285
- Issue date Aug 31, 2010
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Cascaded pass-gate test circuit with interposed split-output drive...
- Patent number 7,782,092
- Issue date Aug 24, 2010
- International Business Machines Corporation
- Ching-Te Chuang
- G01 - MEASURING TESTING
Information Patent Grant
Computer-readable medium encoding a back-gate controlled asymmetric...
- Patent number 7,742,327
- Issue date Jun 22, 2010
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits and methods for characterizing device variation in electro...
- Patent number 7,673,195
- Issue date Mar 2, 2010
- International Business Machines Corporation
- Ching-Te K. Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits and design structures for monitoring NBTI (negative bias t...
- Patent number 7,642,864
- Issue date Jan 5, 2010
- International Business Machines Corporation
- Ching-Te K. Chuang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for determining the slew rate of a signal prod...
- Patent number 7,548,822
- Issue date Jun 16, 2009
- International Business Machines Corporation
- Ching-Te K. Chuang
- G01 - MEASURING TESTING
Information Patent Grant
Computer-readable medium encoding a memory using a back-gate contro...
- Patent number 7,492,628
- Issue date Feb 17, 2009
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Independent-gate controlled asymmetrical memory cell and memory usi...
- Patent number 7,417,889
- Issue date Aug 26, 2008
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
High-density logic techniques with reduced-stack multi-gate field e...
- Patent number 7,382,162
- Issue date Jun 3, 2008
- International Business Machines Corporation
- Meng-Hsueh Chiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetrical memory cells and memories using the cells
- Patent number 7,362,606
- Issue date Apr 22, 2008
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Power gating schemes in SOI circuits in hybrid SOI-epitaxial CMOS s...
- Patent number 7,342,287
- Issue date Mar 11, 2008
- International Business Machines Corporation
- Ching-Te Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual gate transistor keeper dynamic logic
- Patent number 7,336,105
- Issue date Feb 26, 2008
- International Business Machines Corporation
- Ching-Te Chuang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cascaded pass-gate test circuit with interposed split-output drive...
- Patent number 7,323,908
- Issue date Jan 29, 2008
- International Business Machines Corporation
- Ching-Te Chuang
- G01 - MEASURING TESTING
Information Patent Grant
Back-gate controlled asymmetrical memory cell and memory using the...
- Patent number 7,313,012
- Issue date Dec 25, 2007
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-gate dynamic logic circuit with pre-charge keeper
- Patent number 7,298,176
- Issue date Nov 20, 2007
- International Business Machines Corporation
- Hung C. Ngo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High performance PFET header in hybrid orientation technology for l...
- Patent number 7,274,217
- Issue date Sep 25, 2007
- International Business Machines Corporation
- Ching-Te Kent Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Independent gate control logic circuitry
- Patent number 7,265,589
- Issue date Sep 4, 2007
- International Business Machines Corporation
- Ching-Te Chuang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Back-gate controlled read SRAM cell
- Patent number 7,177,177
- Issue date Feb 13, 2007
- International Business Machines Corporation
- Ching-Te Kent Chuang
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense-amp based adder with source follower pass gate evaluation tree
- Patent number 7,085,798
- Issue date Aug 1, 2006
- International Business Machines Corporation
- Jae-Joon Kim
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Design Structure for High Density Stable Static Random Access Memory
- Publication number 20120205721
- Publication date Aug 16, 2012
- International Business Machines Corporation
- Ching-Te K. Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Enhanced Static Random Access Memory Stability Using Asymmetric Acc...
- Publication number 20120185817
- Publication date Jul 19, 2012
- International Business Machines Corporation
- Aditya Bansal
- G11 - INFORMATION STORAGE
Information Patent Application
Techniques for Pattern Process Tuning and Design Optimization for M...
- Publication number 20110173577
- Publication date Jul 14, 2011
- International Business Machines Corporation
- Ching-Te K. Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD E...
- Publication number 20100026346
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Meng-Hsueh Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CI...
- Publication number 20090310430
- Publication date Dec 17, 2009
- International Business Machines Corporation
- Ching-Te K. Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
Methods and Apparatus for Varying a Supply Voltage or Reference Vol...
- Publication number 20090302929
- Publication date Dec 10, 2009
- International Business Machines Corporation
- Ching-Te Kent Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC
- Publication number 20090302894
- Publication date Dec 10, 2009
- International Business Machines Corporation
- Ching-Te Chuang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
High Density Stable Static Random Access Memory
- Publication number 20090302354
- Publication date Dec 10, 2009
- International Business Machines Corporation
- Ching-Te K. Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and Apparatus for Varying a Supply Voltage or Reference Vol...
- Publication number 20090303778
- Publication date Dec 10, 2009
- International Business Machines Corporation
- Ching-Te Kent Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUITS AND DESIGN STRUCTURES FOR MONITORING NBTI (NEGATIVE BIAS T...
- Publication number 20090189703
- Publication date Jul 30, 2009
- International Business Machines Corporation
- Ching-Te K. Chuang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUITS, METHODS AND DESIGN STRUCTURES FOR ADAPTIVE REPAIR OF SRAM...
- Publication number 20090190426
- Publication date Jul 30, 2009
- International Business Machines Corporation
- Ching-Te K. Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCED STATIC RANDOM ACCESS MEMORY STABILITY USING ASYMMETRIC ACC...
- Publication number 20090185409
- Publication date Jul 23, 2009
- International Business Machines Corporation
- Aditya Bansal
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRO...
- Publication number 20090091346
- Publication date Apr 9, 2009
- International Business Machines Corporation
- Ching-Te K. Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTER-READABLE MEDIUM ENCODING A BACK-GATE CONTROLLED ASYMMETRIC...
- Publication number 20090067223
- Publication date Mar 12, 2009
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR DETERMINING THE SLEW RATE OF A SIGNAL PROD...
- Publication number 20090018787
- Publication date Jan 15, 2009
- International Business Machines Corporation
- Ching-Te K. Chuang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INDEPENDENT-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USI...
- Publication number 20080278992
- Publication date Nov 13, 2008
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
CASCADED PASS-GATE TEST CIRCUIT WITH INTERPOSED SPLIT-OUTPUT DRIVE...
- Publication number 20080201672
- Publication date Aug 21, 2008
- Ching-Te Chuang
- G01 - MEASURING TESTING
Information Patent Application
ASYMMETRICAL MEMORY CELLS AND MEMORIES USING THE CELLS
- Publication number 20080144362
- Publication date Jun 19, 2008
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
BACK-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE...
- Publication number 20080084733
- Publication date Apr 10, 2008
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
Asymmetrical memory cells and memories using the cells
- Publication number 20070236982
- Publication date Oct 11, 2007
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
Independent-gate controlled asymmetrical memory cell and memory usi...
- Publication number 20070201261
- Publication date Aug 30, 2007
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
Back-gate controlled asymmetrical memory cell and memory using the...
- Publication number 20070201273
- Publication date Aug 30, 2007
- International Business Machines Corporation
- Ching-Te Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
Cascaded pass-gate test circuit with interposed split-output drive...
- Publication number 20070096770
- Publication date May 3, 2007
- Ching-Te Chuang
- G01 - MEASURING TESTING
Information Patent Application
Methods and apparatus for varying a supply voltage or reference vol...
- Publication number 20070047364
- Publication date Mar 1, 2007
- International Business Machines Corporation
- Ching-Te Kent Chuang
- G11 - INFORMATION STORAGE
Information Patent Application
Dual-gate dynamic logic circuit with pre-charge keeper
- Publication number 20070040584
- Publication date Feb 22, 2007
- Hung C. Ngo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Voltage controlled oscillator using dual gated asymmetrical FET dev...
- Publication number 20070040621
- Publication date Feb 22, 2007
- Hung C. Ngo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Power gating schemes in SOI circuits in hybrid SOI-epitaxial CMOS s...
- Publication number 20070018248
- Publication date Jan 25, 2007
- International Business Machines Corporation
- Ching-Te Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High-density logic techniques with reduced-stack multi-gate field e...
- Publication number 20070013413
- Publication date Jan 18, 2007
- International Business Machines Corporation
- Meng-Hsueh Chiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Independent gate control logic circuitry
- Publication number 20060290384
- Publication date Dec 28, 2006
- Ching-Te Chuang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Dual gate dynamic logic
- Publication number 20060290383
- Publication date Dec 28, 2006
- Ching-Te Chuang
- H03 - BASIC ELECTRONIC CIRCUITRY

Ching-Te Kent Chuang

Person

Patents Grantslast 30 patents

Methods and apparatus for varying a supply voltage or reference vol...

Enhanced static random access memory stability using asymmetric acc...

Structure for high density stable static random access memory

High density stable static random access memory

Enhanced static random access memory stability using asymmetric acc...

Methods for characterizing device variation in electronic memory ci...

High-density logic techniques with reduced-stack multi-gate field e...

High-density low-power data retention power gating with double-gate...

Methods and apparatus for varying a supply voltage or reference vol...

Asymmetrical memory cells and memories using the cells

Dual gate transistor keeper dynamic logic

Independent-gate controlled asymmetrical memory cell and memory usi...

Cascaded pass-gate test circuit with interposed split-output drive...

Computer-readable medium encoding a back-gate controlled asymmetric...

Circuits and methods for characterizing device variation in electro...

Circuits and design structures for monitoring NBTI (negative bias t...

Apparatus and method for determining the slew rate of a signal prod...

Computer-readable medium encoding a memory using a back-gate contro...

Independent-gate controlled asymmetrical memory cell and memory usi...

High-density logic techniques with reduced-stack multi-gate field e...

Asymmetrical memory cells and memories using the cells

Power gating schemes in SOI circuits in hybrid SOI-epitaxial CMOS s...

Dual gate transistor keeper dynamic logic

Cascaded pass-gate test circuit with interposed split-output drive...

Back-gate controlled asymmetrical memory cell and memory using the...

Dual-gate dynamic logic circuit with pre-charge keeper

High performance PFET header in hybrid orientation technology for l...

Independent gate control logic circuitry

Back-gate controlled read SRAM cell

Sense-amp based adder with source follower pass gate evaluation tree

Patents Applicationslast 30 patents

Design Structure for High Density Stable Static Random Access Memory

Enhanced Static Random Access Memory Stability Using Asymmetric Acc...

Techniques for Pattern Process Tuning and Design Optimization for M...

HIGH-DENSITY LOGIC TECHNIQUES WITH REDUCED-STACK MULTI-GATE FIELD E...

METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CI...

Methods and Apparatus for Varying a Supply Voltage or Reference Vol...

DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC

High Density Stable Static Random Access Memory

Methods and Apparatus for Varying a Supply Voltage or Reference Vol...

CIRCUITS AND DESIGN STRUCTURES FOR MONITORING NBTI (NEGATIVE BIAS T...

CIRCUITS, METHODS AND DESIGN STRUCTURES FOR ADAPTIVE REPAIR OF SRAM...

ENHANCED STATIC RANDOM ACCESS MEMORY STABILITY USING ASYMMETRIC ACC...

CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRO...

COMPUTER-READABLE MEDIUM ENCODING A BACK-GATE CONTROLLED ASYMMETRIC...

APPARATUS AND METHOD FOR DETERMINING THE SLEW RATE OF A SIGNAL PROD...

INDEPENDENT-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USI...

CASCADED PASS-GATE TEST CIRCUIT WITH INTERPOSED SPLIT-OUTPUT DRIVE...

ASYMMETRICAL MEMORY CELLS AND MEMORIES USING THE CELLS

BACK-GATE CONTROLLED ASYMMETRICAL MEMORY CELL AND MEMORY USING THE...

Asymmetrical memory cells and memories using the cells

Independent-gate controlled asymmetrical memory cell and memory usi...

Back-gate controlled asymmetrical memory cell and memory using the...

Cascaded pass-gate test circuit with interposed split-output drive...

Methods and apparatus for varying a supply voltage or reference vol...

Dual-gate dynamic logic circuit with pre-charge keeper

Voltage controlled oscillator using dual gated asymmetrical FET dev...

Power gating schemes in SOI circuits in hybrid SOI-epitaxial CMOS s...

High-density logic techniques with reduced-stack multi-gate field e...

Independent gate control logic circuitry

Dual gate dynamic logic