Ching-Tsun Chou

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Processors, methods, systems, and instruction conversion modules fo...
- Patent number 10,761,849
- Issue date Sep 1, 2020
- Intel Corporation
- Ching-Tsun Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Eliminating redundant store instructions from execution while maint...
- Patent number 10,120,686
- Issue date Nov 6, 2018
- Intel Corporation
- Vineeth Mekkat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Satisfying memory ordering requirements between partial reads and n...
- Patent number 10,019,366
- Issue date Jul 10, 2018
- Intel Corporation
- Robert H. Beers
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Satisfying memory ordering requirements between partial reads and n...
- Patent number 9,703,712
- Issue date Jul 11, 2017
- Intel Corporation
- Robert H. Beers
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Satisfying memory ordering requirements between partial reads and n...
- Patent number 9,058,271
- Issue date Jun 16, 2015
- Intel Corporation
- Robert H. Beers
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Satisfying memory ordering requirements between partial reads and n...
- Patent number 8,694,736
- Issue date Apr 8, 2014
- Intel Corporation
- Robert H. Beers
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Scheme for avoiding deadlock in multi-ring interconnect, with addit...
- Patent number 8,693,319
- Issue date Apr 8, 2014
- Intel Corporation
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methodology and tools for tabled-based protocol specification and m...
- Patent number 8,443,337
- Issue date May 14, 2013
- Intel Corporation
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Satisfying memory ordering requirements between partial reads and n...
- Patent number 8,250,311
- Issue date Aug 21, 2012
- Intel Corporation
- Robert H. Beers
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Satisfying memory ordering requirements between partial writes and...
- Patent number 8,205,045
- Issue date Jun 19, 2012
- Intel Corporation
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fairness mechanism for starvation prevention in directory-based cac...
- Patent number 8,099,558
- Issue date Jan 17, 2012
- SeungJoon Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link level retry scheme
- Patent number 7,991,875
- Issue date Aug 2, 2011
- Intel Corporation
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Link level retry scheme
- Patent number 7,016,304
- Issue date Mar 21, 2006
- Intel Corporation
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Acoustic transducer for acoustic microscopy
- Patent number 4,909,082
- Issue date Mar 20, 1990
- The Board of Trustees of the Leland Stanford Junior University
- Butrus T. Khuri-Yakub
- G10 - MUSICAL INSTRUMENTS ACOUSTICS

Patents Applicationslast 30 patents

Information Patent Application
DIRECT, UNCONDITIONAL JUMP
- Publication number 20250028532
- Publication date Jan 23, 2025
- Intel Corporation
- Jason AGRON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS AND SUPPORT FOR CONDITIONAL COMPARISON AND TEST
- Publication number 20240220262
- Publication date Jul 4, 2024
- Jason AGRON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFIX EXTENSIONS FOR EXTENDED GENERAL PURPOSE REGISTERS WITH OPTIM...
- Publication number 20240220260
- Publication date Jul 4, 2024
- Jason AGRON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS AND SUPPORT FOR STACK PUSH AND POP
- Publication number 20240220257
- Publication date Jul 4, 2024
- Jason AGRON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS AND SUPPORT FOR CONDITIONAL LOAD AND STORE
- Publication number 20240220261
- Publication date Jul 4, 2024
- Jason AGRON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTION CONVERSION MODULES FO...
- Publication number 20180081684
- Publication date Mar 22, 2018
- Intel Corporation
- Ching-Tsun Chou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for Total Store Elimination
- Publication number 20170351516
- Publication date Dec 7, 2017
- Intel Corporation
- Vineeth Mekkat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...
- Publication number 20170308471
- Publication date Oct 26, 2017
- Intel Corporation
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...
- Publication number 20150178210
- Publication date Jun 25, 2015
- Intel Corporation
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...
- Publication number 20140115275
- Publication date Apr 24, 2014
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCHEME FOR AVOIDING DEADLOCK IN MULTI-RING INTERCONNECT, WITH ADDIT...
- Publication number 20140112145
- Publication date Apr 24, 2014
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...
- Publication number 20120317369
- Publication date Dec 13, 2012
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAIRNESS MECHANISM FOR STARVATION PREVENTION IN DIRECTORY-BASED CAC...
- Publication number 20100250861
- Publication date Sep 30, 2010
- Seungjoon Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCHEME FOR AVOIDING DEADLOCK IN MULTI-RING INTERCONNECT, WITH ADDIT...
- Publication number 20100074106
- Publication date Mar 25, 2010
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL WRITES AND...
- Publication number 20100005245
- Publication date Jan 7, 2010
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...
- Publication number 20100005246
- Publication date Jan 7, 2010
- Robert H. Beers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE CACHE ORGANIZATION FOR CHIP MULTIPROCESSORS
- Publication number 20090254712
- Publication date Oct 8, 2009
- Naveen Cherukuri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methodology and tools for table-based protocol specification and mo...
- Publication number 20090235228
- Publication date Sep 17, 2009
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTERCONNECT ARCHITECTURAL STATE COVERAGE MEASUREMENT METHODOLOGY
- Publication number 20090171647
- Publication date Jul 2, 2009
- Phanindra Mannava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Link level retry scheme
- Publication number 20070130353
- Publication date Jun 7, 2007
- Intel Corporation
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Link level retry scheme
- Publication number 20020172164
- Publication date Nov 21, 2002
- Ching-Tsun Chou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Ching-Tsun Chou

Person

Patents Grantslast 30 patents

Processors, methods, systems, and instruction conversion modules fo...

Eliminating redundant store instructions from execution while maint...

Satisfying memory ordering requirements between partial reads and n...

Satisfying memory ordering requirements between partial reads and n...

Satisfying memory ordering requirements between partial reads and n...

Satisfying memory ordering requirements between partial reads and n...

Scheme for avoiding deadlock in multi-ring interconnect, with addit...

Methodology and tools for tabled-based protocol specification and m...

Satisfying memory ordering requirements between partial reads and n...

Satisfying memory ordering requirements between partial writes and...

Fairness mechanism for starvation prevention in directory-based cac...

Link level retry scheme

Link level retry scheme

Acoustic transducer for acoustic microscopy

Patents Applicationslast 30 patents

DIRECT, UNCONDITIONAL JUMP

INSTRUCTIONS AND SUPPORT FOR CONDITIONAL COMPARISON AND TEST

PREFIX EXTENSIONS FOR EXTENDED GENERAL PURPOSE REGISTERS WITH OPTIM...

INSTRUCTIONS AND SUPPORT FOR STACK PUSH AND POP

INSTRUCTIONS AND SUPPORT FOR CONDITIONAL LOAD AND STORE

PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTION CONVERSION MODULES FO...

Instruction and Logic for Total Store Elimination

SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...

SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...

SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...

SCHEME FOR AVOIDING DEADLOCK IN MULTI-RING INTERCONNECT, WITH ADDIT...

SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...

FAIRNESS MECHANISM FOR STARVATION PREVENTION IN DIRECTORY-BASED CAC...

SCHEME FOR AVOIDING DEADLOCK IN MULTI-RING INTERCONNECT, WITH ADDIT...

SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL WRITES AND...

SATISFYING MEMORY ORDERING REQUIREMENTS BETWEEN PARTIAL READS AND N...

ADAPTIVE CACHE ORGANIZATION FOR CHIP MULTIPROCESSORS

Methodology and tools for table-based protocol specification and mo...

INTERCONNECT ARCHITECTURAL STATE COVERAGE MEASUREMENT METHODOLOGY

Link level retry scheme

Link level retry scheme