Chinsong Sul

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low cost design for test architecture
- Patent number 11,144,696
- Issue date Oct 12, 2021
- Chinsong Sul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low cost design for test architecture
- Patent number 10,712,388
- Issue date Jul 14, 2020
- Chinsong Sul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low cost design for test architecture
- Patent number 10,338,138
- Issue date Jul 2, 2019
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Grant
Test solution for a random number generator
- Patent number 9,231,567
- Issue date Jan 5, 2016
- LATTICE SEMICONDUCTOR CORPORATION
- Chinsong Sul
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Computer memory test structure
- Patent number 8,924,805
- Issue date Dec 30, 2014
- Silicon Image, Inc.
- Chinsong Sul
- G11 - INFORMATION STORAGE
Information Patent Grant
Test solution for ring oscillators
- Patent number 8,841,974
- Issue date Sep 23, 2014
- Silicon Image, Inc.
- Chinsong Sul
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-site testing of computer memory devices and serial IO ports
- Patent number 8,839,058
- Issue date Sep 16, 2014
- Silicon Image, Inc.
- Chinsong Sul
- G11 - INFORMATION STORAGE
Information Patent Grant
Computer memory test structure
- Patent number 8,667,354
- Issue date Mar 4, 2014
- Silicon Image, Inc.
- Chinsong Sul
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing of high-speed input-output devices
- Patent number 8,598,898
- Issue date Dec 3, 2013
- Silicon Image, Inc.
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Grant
Multi-site testing of computer memory devices and serial IO ports
- Patent number 8,543,873
- Issue date Sep 24, 2013
- Silicon Image, Inc.
- Chinsong Sul
- G11 - INFORMATION STORAGE
Information Patent Grant
Computer memory test structure
- Patent number 8,386,867
- Issue date Feb 26, 2013
- Silicon Image, Inc.
- Chinsong Sul
- G11 - INFORMATION STORAGE
Information Patent Grant
Fault testing for interconnections
- Patent number 8,026,726
- Issue date Sep 27, 2011
- Silicon Image, Inc.
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Grant
Concurrent code checker and hardware efficient high-speed I/O havin...
- Patent number 7,984,369
- Issue date Jul 19, 2011
- Silicon Image, Inc.
- Chinsong Sul
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scan-based testing of devices implementing a test clock control str...
- Patent number 7,840,861
- Issue date Nov 23, 2010
- Silicon Image, Inc.
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Grant
Circuitry to prevent peak power problems during scan shift
- Patent number 7,831,877
- Issue date Nov 9, 2010
- Silicon Image, Inc.
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Grant
Test clock control structures to generate configurable test clocks...
- Patent number 7,793,179
- Issue date Sep 7, 2010
- Silicon Image, Inc.
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Grant
Interface test circuitry and methods
- Patent number 7,698,088
- Issue date Apr 13, 2010
- Silicon Image, Inc.
- Chinsong Sul
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hierarchical creation of vectors for quiescent current (IDDQ) tests...
- Patent number 6,751,768
- Issue date Jun 15, 2004
- Agilent Technologies, Inc.
- Fidel Muradali
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Low Cost Design For Test Architecture
- Publication number 20190324083
- Publication date Oct 24, 2019
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
Low Cost Design for Test Architecture
- Publication number 20170193154
- Publication date Jul 6, 2017
- Chinsong Sul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test Solution for a Random Number Generator
- Publication number 20140191813
- Publication date Jul 10, 2014
- Silicon Image, Inc.
- Chinsong Sul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER MEMORY TEST STRUCTURE
- Publication number 20140115414
- Publication date Apr 24, 2014
- Silicon Image, Inc.
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
TEST SOLUTION FOR RING OSCILLATORS
- Publication number 20140062606
- Publication date Mar 6, 2014
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS
- Publication number 20140026006
- Publication date Jan 23, 2014
- Silicon Image, Inc.
- Chinsong Sul
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTER MEMORY TEST STRUCTURE
- Publication number 20130173974
- Publication date Jul 4, 2013
- Silicon Image, Inc.
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
IDDQ TESTING OF CMOS DEVICES
- Publication number 20120158346
- Publication date Jun 21, 2012
- Silicon Image, Inc.
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
TESTING OF HIGH-SPEED INPUT-OUTPUT DEVICES
- Publication number 20120081138
- Publication date Apr 5, 2012
- Silicon Image, Inc.
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS
- Publication number 20110167308
- Publication date Jul 7, 2011
- Chinsong Sul
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTER MEMORY TEST STRUCTURE
- Publication number 20110004793
- Publication date Jan 6, 2011
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
FAULT TESTING FOR INTERCONNECTIONS
- Publication number 20100188097
- Publication date Jul 29, 2010
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
CIRCUITRY TO PREVENT PEAK POWER PROBLEMS DURING SCAN SHIFT
- Publication number 20080222471
- Publication date Sep 11, 2008
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
INTERFACE TEST CIRCUITRY AND METHODS
- Publication number 20080114562
- Publication date May 15, 2008
- Chinsong Sul
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Test clock control structures to generate configurable test clocks...
- Publication number 20080010573
- Publication date Jan 10, 2008
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
Scan-based testing of devices implementing a test clock control str...
- Publication number 20080010572
- Publication date Jan 10, 2008
- Chinsong Sul
- G01 - MEASURING TESTING
Information Patent Application
Concurrent code checker and hardware efficient high-speed I/O havin...
- Publication number 20070204204
- Publication date Aug 30, 2007
- Chinsong Sul
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for improved accuracy of standard cell timing models
- Publication number 20040215437
- Publication date Oct 28, 2004
- Chinsong Sul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hierarchical creation of vectors for quiescent current (IDDQ) tests...
- Publication number 20030101398
- Publication date May 29, 2003
- Fidel Muradali
- G01 - MEASURING TESTING

Chinsong Sul

Person

Patents Grantslast 30 patents

Low cost design for test architecture

Low cost design for test architecture

Low cost design for test architecture

Test solution for a random number generator

Computer memory test structure

Test solution for ring oscillators

Multi-site testing of computer memory devices and serial IO ports

Computer memory test structure

Testing of high-speed input-output devices

Multi-site testing of computer memory devices and serial IO ports

Computer memory test structure

Fault testing for interconnections

Concurrent code checker and hardware efficient high-speed I/O havin...

Scan-based testing of devices implementing a test clock control str...

Circuitry to prevent peak power problems during scan shift

Test clock control structures to generate configurable test clocks...

Interface test circuitry and methods

Hierarchical creation of vectors for quiescent current (IDDQ) tests...

Patents Applicationslast 30 patents

Low Cost Design For Test Architecture

Low Cost Design for Test Architecture

Test Solution for a Random Number Generator

COMPUTER MEMORY TEST STRUCTURE

TEST SOLUTION FOR RING OSCILLATORS

MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS

COMPUTER MEMORY TEST STRUCTURE

IDDQ TESTING OF CMOS DEVICES

TESTING OF HIGH-SPEED INPUT-OUTPUT DEVICES

MULTI-SITE TESTING OF COMPUTER MEMORY DEVICES AND SERIAL IO PORTS

COMPUTER MEMORY TEST STRUCTURE

FAULT TESTING FOR INTERCONNECTIONS

CIRCUITRY TO PREVENT PEAK POWER PROBLEMS DURING SCAN SHIFT

INTERFACE TEST CIRCUITRY AND METHODS

Test clock control structures to generate configurable test clocks...

Scan-based testing of devices implementing a test clock control str...

Concurrent code checker and hardware efficient high-speed I/O havin...

System and method for improved accuracy of standard cell timing models

Hierarchical creation of vectors for quiescent current (IDDQ) tests...