Chiu-Yu Ku

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Taipei, TW

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Patents Grantslast 30 patents

Information Patent Grant
Circuit layout verification
- Patent number 11,734,489
- Issue date Aug 22, 2023
- Synopsys, Inc.
- Jinsik Yun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout-versus-schematic (LVS) debugging and error diagnosis via typ...
- Patent number 11,341,310
- Issue date May 24, 2022
- Synopsys, Inc.
- Chiu-Yu Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying root cause of layout versus schematic errors
- Patent number 10,970,456
- Issue date Apr 6, 2021
- Synopsys, Inc.
- Wei-shun Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying root cause of layout versus schematic errors
- Patent number 10,691,867
- Issue date Jun 23, 2020
- Synopsys, Inc.
- Wei-shun Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus used for the physical validation of integrated...
- Patent number 8,826,219
- Issue date Sep 2, 2014
- Synopsys, Inc.
- Chiu-Yu Ku
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CIRCUIT LAYOUT VERIFICATION
- Publication number 20210374322
- Publication date Dec 2, 2021
- Synopsys, Inc.
- Jinsik Yun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IDENTIFYING ROOT CAUSE OF LAYOUT VERSUS SCHEMATIC ERRORS
- Publication number 20190065660
- Publication date Feb 28, 2019
- Synopsys, Inc.
- Wei-shun Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus Used for the Physical Validation of Integrated...
- Publication number 20120216162
- Publication date Aug 23, 2012
- Synopsys, Inc.
- Chiu-Yu Ku
- G06 - COMPUTING CALCULATING COUNTING