Chiyi Kao

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Alternate pad structures/passivation inegration schemes to reduce o...
- Patent number 8,552,560
- Issue date Oct 8, 2013
- LSI Corporation
- Hemanshu Bhatt
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Reduction of macro level stresses in copper/low-K wafers
- Patent number 8,076,779
- Issue date Dec 13, 2011
- LSI Corporation
- Sey-Shing Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Eliminate IMC cracking in post wirebonded dies: macro level stress...
- Patent number 7,531,442
- Issue date May 12, 2009
- LSI Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduce or eliminate IMC cracking in post wire bonded dies by doping...
- Patent number 7,205,673
- Issue date Apr 17, 2007
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Eliminate IMC cracking in post wirebonded dies: macro level stress...
- Publication number 20070123024
- Publication date May 31, 2007
- LSI Logic Corporation
- Jayanthi Pallinti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Alternate pad structures/passivation inegration schemes to reduce o...
- Publication number 20070114667
- Publication date May 24, 2007
- LSI Logic Corporation
- Hemanshu Bhatt
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Reduction of macro level stresses in copper/Low-K wafers by alterin...
- Publication number 20070102812
- Publication date May 10, 2007
- LSI Logic Corporation
- Sey-Shing Sun
- H01 - BASIC ELECTRIC ELEMENTS