Cho Moon

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Timing-aware surgical optimization for engineering change order in...
- Patent number 12,175,181
- Issue date Dec 24, 2024
- Synopsys, Inc.
- Bon Woong Ku
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic reduction of modes of electronic circuits for timing anal...
- Patent number 8,701,074
- Issue date Apr 15, 2014
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic generation of merged mode constraints for electronic circ...
- Patent number 8,627,262
- Issue date Jan 7, 2014
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic verification of merged mode constraints for electronic ci...
- Patent number 8,607,186
- Issue date Dec 10, 2013
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Comparing timing constraints of circuits
- Patent number 8,261,221
- Issue date Sep 4, 2012
- Synopsys, Inc.
- Sonia Singhal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of designing a digital circuit by correlating different stat...
- Patent number 7,823,098
- Issue date Oct 26, 2010
- Tela Innovations, Inc.
- Cho W. Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatus to perform static timing analysis a...
- Patent number 7,418,684
- Issue date Aug 26, 2008
- Cadence Design Systems, Inc.
- Cho W. Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assertion handling for timing model extraction
- Patent number 7,356,451
- Issue date Apr 8, 2008
- Cadence Design Systems, Inc.
- Cho Woo Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing model extraction by timing graph reduction
- Patent number 6,928,630
- Issue date Aug 9, 2005
- Cadence Design Systems, Inc.
- Cho Woo Moon
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AUTOMATIC REDUCTION OF MODES OF ELECTRONIC CIRCUITS FOR TIMING ANAL...
- Publication number 20120324410
- Publication date Dec 20, 2012
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC GENERATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRC...
- Publication number 20110252393
- Publication date Oct 13, 2011
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPARING TIMING CONSTRAINTS OF CIRCUITS
- Publication number 20110252388
- Publication date Oct 13, 2011
- Synopsys, Inc.
- Sonia Singhal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC VERIFICATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CI...
- Publication number 20110252390
- Publication date Oct 13, 2011
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Timing model extraction by timing graph reduction
- Publication number 20030121013
- Publication date Jun 26, 2003
- Cadence Design Systems, Inc.
- Cho Woo Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Assertion handling for timing model extraction
- Publication number 20030120474
- Publication date Jun 26, 2003
- Cadence Design Systems, Inc.
- Cho Woo Moon
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Timing-aware surgical optimization for engineering change order in...

Automatic reduction of modes of electronic circuits for timing anal...

Automatic generation of merged mode constraints for electronic circ...

Automatic verification of merged mode constraints for electronic ci...

Comparing timing constraints of circuits

Method of designing a digital circuit by correlating different stat...

Systems, methods, and apparatus to perform static timing analysis a...

Assertion handling for timing model extraction

Timing model extraction by timing graph reduction

Patents Applicationslast 30 patents

AUTOMATIC REDUCTION OF MODES OF ELECTRONIC CIRCUITS FOR TIMING ANAL...

AUTOMATIC GENERATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRC...

COMPARING TIMING CONSTRAINTS OF CIRCUITS

AUTOMATIC VERIFICATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CI...

Timing model extraction by timing graph reduction

Assertion handling for timing model extraction