Chong J. Zhao

Person

West Linn, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Techniques to couple high bandwidth memory device on silicon substr...
- Patent number 12,087,352
- Issue date Sep 10, 2024
- Tahoe Research, LTD.
- Chong J. Zhao
- G11 - INFORMATION STORAGE
Information Patent Grant
Package pin pattern for device-to-device connection
- Patent number 12,073,906
- Issue date Aug 27, 2024
- Intel Corporation
- Chong J. Zhao
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to couple high bandwidth memory device on silicon substr...
- Patent number 11,776,619
- Issue date Oct 3, 2023
- Tahoe Research, LTD.
- Chong J. Zhao
- G11 - INFORMATION STORAGE
Information Patent Grant
Interposer and electronic package
- Patent number 11,621,237
- Issue date Apr 4, 2023
- Intel Corporation
- Jonathan W. Thibado
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated memory coplanar transmission line package having ground...
- Patent number 11,569,161
- Issue date Jan 31, 2023
- Intel Corporation
- Chong Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques to couple high bandwidth memory device on silicon substr...
- Patent number 11,557,333
- Issue date Jan 17, 2023
- Tahoe Research, LTD.
- Chong J. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques to couple high bandwidth memory device on silicon substr...
- Patent number 11,056,179
- Issue date Jul 6, 2021
- Intel Corporation
- Chong J. Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DIMM for a high bandwidth memory channel
- Patent number 10,884,958
- Issue date Jan 5, 2021
- Intel Corporation
- Rajat Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to access or operate a dual in-line memory module via mu...
- Patent number 10,592,445
- Issue date Mar 17, 2020
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to access or operate a dual in-line memory module via mu...
- Patent number 10,146,711
- Issue date Dec 4, 2018
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shielded high density card connector
- Patent number 9,929,511
- Issue date Mar 27, 2018
- Intel Corporation
- John M. Lynch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CPU package substrates with removable memory mechanical interfaces
- Patent number 9,832,876
- Issue date Nov 28, 2017
- Intel Corporation
- Mani Prakash
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Devices and methods to reduce differential signal pair crosstalk
- Patent number 9,554,454
- Issue date Jan 24, 2017
- Intel Corporation
- Chong Richard Zhao
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...
- Publication number 20250006250
- Publication date Jan 2, 2025
- Tahoe Research, Ltd.
- Chong J. ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCED I/O SEMICONDUCTOR CHIP PACKAGE AND COOLING ASSEMBLY HAVING...
- Publication number 20240421025
- Publication date Dec 19, 2024
- Intel Corporation
- Lianchang DU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...
- Publication number 20240029785
- Publication date Jan 25, 2024
- Tahoe Research, Ltd.
- Chong J. ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...
- Publication number 20230145937
- Publication date May 11, 2023
- Tahoe Research, Ltd.
- Chong J. ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...
- Publication number 20210335414
- Publication date Oct 28, 2021
- Intel Corporation
- Chong J. ZHAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED MEMORY CHIP SOLUTION WITH REDUCED PACKAGE INPUTS/OUTPUTS (I...
- Publication number 20210335393
- Publication date Oct 28, 2021
- Intel Corporation
- Chong J. ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
PACKAGE PIN PATTERN FOR DEVICE-TO-DEVICE CONNECTION
- Publication number 20210074333
- Publication date Mar 11, 2021
- Intel Corporation
- Chong J. ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED MEMORY COPLANAR TRANSMISSION LINE PACKAGE TO EXTEND MEMO...
- Publication number 20200243433
- Publication date Jul 30, 2020
- Chong ZHAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REFLOWABLE GRID ARRAY WITH HIGH SPEED FLEX CABLES
- Publication number 20200227362
- Publication date Jul 16, 2020
- Intel Corporation
- Jonathan W. THIBADO
- G02 - OPTICS
Information Patent Application
TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...
- Publication number 20200143870
- Publication date May 7, 2020
- Intel Corporation
- Chong J. ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES TO ACCESS OR OPERATE A DUAL IN-LINE MEMORY MODULE VIA MU...
- Publication number 20190213148
- Publication date Jul 11, 2019
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BACK-END MEMORY CHANNEL THAT RESIDES BETWEEN FIRST AND SECOND DIMM...
- Publication number 20190042162
- Publication date Feb 7, 2019
- Intel Corporationn
- James A. McCALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONNECTOR, BOARD ASSEMBLY, COMPUTING SYSTEM, AND METHODS THEREOF
- Publication number 20190045632
- Publication date Feb 7, 2019
- Intel Corporation
- Xiang Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIMM FOR A HIGH BANDWIDTH MEMORY CHANNEL
- Publication number 20190042500
- Publication date Feb 7, 2019
- Intel Corporation
- Rajat AGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CPU PACKAGE SUBSTRATES WITH REMOVABLE MEMORY MECHANICAL INTERFACES
- Publication number 20180007791
- Publication date Jan 4, 2018
- Intel Corporation
- Mani Prakash
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHIELDED HIGH DENSITY CARD CONNECTOR
- Publication number 20170271818
- Publication date Sep 21, 2017
- Intel Corporation
- John M. Lynch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Techniques to Access or Operate a Dual In-Line Memory Module via Mu...
- Publication number 20170199830
- Publication date Jul 13, 2017
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CPU PACKAGE SUBSTRATES WITH REMOVABLE MEMORY MECHANICAL INTERFACES
- Publication number 20160183374
- Publication date Jun 23, 2016
- Mani Prakash
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICES AND METHODS TO REDUCE DIFFERENTIAL SIGNAL PAIR CROSSTALK
- Publication number 20160181682
- Publication date Jun 23, 2016
- Chong Richard Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CONNECTOR FOR TWO SODIMM PER CHANNEL CONFIGURATION
- Publication number 20150171535
- Publication date Jun 18, 2015
- Xiang Li
- H01 - BASIC ELECTRIC ELEMENTS

Chong J. Zhao

Person

Patents Grantslast 30 patents

Techniques to couple high bandwidth memory device on silicon substr...

Package pin pattern for device-to-device connection

Techniques to couple high bandwidth memory device on silicon substr...

Interposer and electronic package

Integrated memory coplanar transmission line package having ground...

Techniques to couple high bandwidth memory device on silicon substr...

Techniques to couple high bandwidth memory device on silicon substr...

DIMM for a high bandwidth memory channel

Techniques to access or operate a dual in-line memory module via mu...

Techniques to access or operate a dual in-line memory module via mu...

Shielded high density card connector

CPU package substrates with removable memory mechanical interfaces

Devices and methods to reduce differential signal pair crosstalk

Patents Applicationslast 30 patents

TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...

ENHANCED I/O SEMICONDUCTOR CHIP PACKAGE AND COOLING ASSEMBLY HAVING...

TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...

TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...

TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...

STACKED MEMORY CHIP SOLUTION WITH REDUCED PACKAGE INPUTS/OUTPUTS (I...

PACKAGE PIN PATTERN FOR DEVICE-TO-DEVICE CONNECTION

INTEGRATED MEMORY COPLANAR TRANSMISSION LINE PACKAGE TO EXTEND MEMO...

REFLOWABLE GRID ARRAY WITH HIGH SPEED FLEX CABLES

TECHNIQUES TO COUPLE HIGH BANDWIDTH MEMORY DEVICE ON SILICON SUBSTR...

TECHNIQUES TO ACCESS OR OPERATE A DUAL IN-LINE MEMORY MODULE VIA MU...

BACK-END MEMORY CHANNEL THAT RESIDES BETWEEN FIRST AND SECOND DIMM...

CONNECTOR, BOARD ASSEMBLY, COMPUTING SYSTEM, AND METHODS THEREOF

DIMM FOR A HIGH BANDWIDTH MEMORY CHANNEL

CPU PACKAGE SUBSTRATES WITH REMOVABLE MEMORY MECHANICAL INTERFACES

SHIELDED HIGH DENSITY CARD CONNECTOR

Techniques to Access or Operate a Dual In-Line Memory Module via Mu...

CPU PACKAGE SUBSTRATES WITH REMOVABLE MEMORY MECHANICAL INTERFACES

DEVICES AND METHODS TO REDUCE DIFFERENTIAL SIGNAL PAIR CROSSTALK

MEMORY CONNECTOR FOR TWO SODIMM PER CHANNEL CONFIGURATION