Chong Ming Lin

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Selective power-down for high performance CPU/system
- Patent number 8,117,468
- Issue date Feb 14, 2012
- Chong Ming Lin
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Programmable junction field effect transistor and method for progra...
- Patent number 7,655,964
- Issue date Feb 2, 2010
- Qspeed Semiconductor Inc.
- Chong-Ming Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Clock generator with programmable non-overlapping-clock-edge capabi...
- Patent number 7,642,832
- Issue date Jan 5, 2010
- Seiko Epson Corporation
- Ho Dai Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for manufacturing a power bus on a chip
- Patent number 7,516,436
- Issue date Apr 7, 2009
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective power-down for high performance CPU/system
- Patent number 7,506,185
- Issue date Mar 17, 2009
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock generator with programmable non-overlapping-clock-edge capabi...
- Patent number 7,352,222
- Issue date Apr 1, 2008
- Seiko Epson Corporation
- Ho Dai Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Schottky barrier rectifier and method of manufacturing the same
- Patent number 7,238,976
- Issue date Jul 3, 2007
- Qspeed Semiconductor Inc.
- Ho-Yuan Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for enhanced performance in semiconductor subs...
- Patent number 7,227,242
- Issue date Jun 5, 2007
- Qspeed Semiconductor Inc.
- Chong Ming Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a Schottky barrier rectifier
- Patent number 7,220,661
- Issue date May 22, 2007
- Qspeed Semiconductor Inc.
- Ho-Yuan Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a power bus on a chip
- Patent number 7,103,867
- Issue date Sep 5, 2006
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective power-down for high performance CPU/system
- Patent number 7,082,543
- Issue date Jul 25, 2006
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable junction field effect transistor and method for progra...
- Patent number 7,075,132
- Issue date Jul 11, 2006
- Lovoltech, Inc.
- Chong Ming Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrostatic discharge protection device for integrated circuits
- Patent number 7,009,229
- Issue date Mar 7, 2006
- Lovoltech, Incorporated
- Chong Ming Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Clock generator with programmable non-overlapping-clock-edge capabi...
- Patent number 6,900,682
- Issue date May 31, 2005
- Seiko Epson Corporation
- Ho Dai Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Computer program product for defining slits in a bus on a chip
- Patent number 6,842,885
- Issue date Jan 11, 2005
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective power-down for high performance CPU/system
- Patent number 6,785,761
- Issue date Aug 31, 2004
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electrostatic discharge protection device for integrated circuits
- Patent number 6,774,417
- Issue date Aug 10, 2004
- Lovoltech, Inc.
- Chong Ming Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Clock generator with programmable non-overlapping-clock-edge capabi...
- Patent number 6,653,881
- Issue date Nov 25, 2003
- Seiko Epson Corporation
- Ho Dai Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Selective power-down for high performance CPU/system
- Patent number 6,587,952
- Issue date Jul 1, 2003
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock generator with programmable non-overlapping clock-edge capabi...
- Patent number 6,489,826
- Issue date Dec 3, 2002
- Seiko Epson Corporation
- Ho Dai Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Selective power-down for high performance CPU/system
- Patent number 6,430,693
- Issue date Aug 6, 2002
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power bus and method for generating power slits therein
- Patent number 6,378,120
- Issue date Apr 23, 2002
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock generator with programmable non-overlapping-clock-edge-capabi...
- Patent number 6,323,711
- Issue date Nov 27, 2001
- Seiko Epson Corporation
- Ho Dai Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Selective power-down for high performance CPU/system
- Patent number 6,256,743
- Issue date Jul 3, 2001
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power bus and method for generating power slits therein
- Patent number 6,233,721
- Issue date May 15, 2001
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with hardware-based programmable non-overlapping...
- Patent number 6,163,194
- Issue date Dec 19, 2000
- Seiko Epson Corporation
- Ho Dai Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for manufacturing an integrated circuit with programmable no...
- Patent number 5,966,037
- Issue date Oct 12, 1999
- Seiko Epson Corporation of Tokyo Japan
- Ho Dai Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for manufacturing a power bus on a chip
- Patent number 5,909,377
- Issue date Jun 1, 1999
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Space saving method and floor plan for fabricating an integrated ci...
- Patent number 5,806,084
- Issue date Sep 8, 1998
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective power-down for high performance CPU/system
- Patent number 5,787,297
- Issue date Jul 28, 1998
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Selective Power-Down For High Performance CPU/System
- Publication number 20090228729
- Publication date Sep 10, 2009
- SEIKO EPSON CORPORATION
- Chong Ming LIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Generator With Programmable Non-Overlapping-Clock-Edge Capabi...
- Publication number 20080129360
- Publication date Jun 5, 2008
- SEIKO EPSON CORPORATION
- Ho Dai TRUONG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for manufacturing a power bus on a chip
- Publication number 20060253826
- Publication date Nov 9, 2006
- SEIKO EPSON CORPORATION
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Selective power-down for high performance CPU/system
- Publication number 20060230300
- Publication date Oct 12, 2006
- SEIKO EPSON CORPORATION
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock generator with programmable non-overlapping-clock-edge capabi...
- Publication number 20050189978
- Publication date Sep 1, 2005
- SEIKO EPSON CORPORATION
- Ho Dai Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method for manufacturing a power bus on a chip
- Publication number 20050086625
- Publication date Apr 21, 2005
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock generator with programmable non-overlapping-clock-edge capabi...
- Publication number 20040056699
- Publication date Mar 25, 2004
- Seiko Epson Corporation
- Ho Dai Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Selective power-down for high performance CPU/system
- Publication number 20030196128
- Publication date Oct 16, 2003
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Selective power-down for high performance
- Publication number 20030196129
- Publication date Oct 16, 2003
- Seiko Epson Corporation
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock generator with programmable non-overlapping-clock-edge capabi...
- Publication number 20030058018
- Publication date Mar 27, 2003
- Ho Dai Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SELECTIVE POWER-DOWN FOR HIGH PERFORMANCE CPU/SYSTEM
- Publication number 20020184548
- Publication date Dec 5, 2002
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cumputer Program Product for Defining Slits in a Bus on a Chip
- Publication number 20020078426
- Publication date Jun 20, 2002
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock generator with programmable non-overlapping-clock-edge capabi...
- Publication number 20020017938
- Publication date Feb 14, 2002
- Ho Dai Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Selective power-down for high performance CPU/system
- Publication number 20020013912
- Publication date Jan 31, 2002
- Chong Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power bus and method for generating power slits therein
- Publication number 20010002318
- Publication date May 31, 2001
- Chong M. Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generator with programmable non-overlapping-clock-edge capability
- Publication number 20010000018
- Publication date Mar 15, 2001
- Ho Dai Truong
- H03 - BASIC ELECTRONIC CIRCUITRY

Chong Ming Lin

Person

Patents Grantslast 30 patents

Selective power-down for high performance CPU/system

Programmable junction field effect transistor and method for progra...

Clock generator with programmable non-overlapping-clock-edge capabi...

Method for manufacturing a power bus on a chip

Selective power-down for high performance CPU/system

Clock generator with programmable non-overlapping-clock-edge capabi...

Schottky barrier rectifier and method of manufacturing the same

Structure and method for enhanced performance in semiconductor subs...

Method of manufacturing a Schottky barrier rectifier

Method for manufacturing a power bus on a chip

Selective power-down for high performance CPU/system

Programmable junction field effect transistor and method for progra...

Electrostatic discharge protection device for integrated circuits

Clock generator with programmable non-overlapping-clock-edge capabi...

Computer program product for defining slits in a bus on a chip

Selective power-down for high performance CPU/system

Electrostatic discharge protection device for integrated circuits

Clock generator with programmable non-overlapping-clock-edge capabi...

Selective power-down for high performance CPU/system

Clock generator with programmable non-overlapping clock-edge capabi...

Selective power-down for high performance CPU/system

Power bus and method for generating power slits therein

Clock generator with programmable non-overlapping-clock-edge-capabi...

Selective power-down for high performance CPU/system

Power bus and method for generating power slits therein

Integrated circuit with hardware-based programmable non-overlapping...

Method for manufacturing an integrated circuit with programmable no...

Method for manufacturing a power bus on a chip

Space saving method and floor plan for fabricating an integrated ci...

Selective power-down for high performance CPU/system

Patents Applicationslast 30 patents

Selective Power-Down For High Performance CPU/System

Clock Generator With Programmable Non-Overlapping-Clock-Edge Capabi...

Method for manufacturing a power bus on a chip

Selective power-down for high performance CPU/system

Clock generator with programmable non-overlapping-clock-edge capabi...

Method for manufacturing a power bus on a chip

Clock generator with programmable non-overlapping-clock-edge capabi...

Selective power-down for high performance CPU/system

Selective power-down for high performance

Clock generator with programmable non-overlapping-clock-edge capabi...

SELECTIVE POWER-DOWN FOR HIGH PERFORMANCE CPU/SYSTEM

Cumputer Program Product for Defining Slits in a Bus on a Chip

Clock generator with programmable non-overlapping-clock-edge capabi...

Selective power-down for high performance CPU/system

Power bus and method for generating power slits therein

Generator with programmable non-overlapping-clock-edge capability