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Chooi Pei Lim
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Bayan Lepas, MY
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Patents Grants
last 30 patents
Information
Patent Grant
Techniques for clock signal transmission in integrated circuits and...
Patent number
11,500,412
Issue date
Nov 15, 2022
Intel Corporation
Jeffrey Chromczak
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Clock synchronization in multi-die field programmable gate array de...
Patent number
10,530,367
Issue date
Jan 7, 2020
Intel Corporation
Chooi Pei Lim
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Methods and apparatus for reducing power in clock distribution netw...
Patent number
9,577,649
Issue date
Feb 21, 2017
Altera Corporation
Boon Pin Liong
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Multi-layer distributed network
Patent number
9,430,433
Issue date
Aug 30, 2016
Altera Corporation
Keong Hong Oh
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Mask set for fabricating integrated circuits and method of fabricat...
Patent number
9,401,281
Issue date
Jul 26, 2016
Altera Corporation
Jordan Plofsky
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Stacked integrated circuit with redundancy in die-to-die interconnects
Patent number
9,236,864
Issue date
Jan 12, 2016
Altera Corporation
Siang Poh Loh
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Clock signal networks for structured ASIC devices
Patent number
9,225,335
Issue date
Dec 29, 2015
Altera Corporation
Chooi Pei Lim
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
3D built-in self-test scheme for 3D assembly defect detection
Patent number
8,793,547
Issue date
Jul 29, 2014
Altera Corporation
Siang Poh Loh
G01 - MEASURING TESTING
Information
Patent Grant
Method and apparatus for providing signal routing control
Patent number
8,786,308
Issue date
Jul 22, 2014
Altera Corporation
Siang Poh Loh
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Systems including an I/O stack and methods for fabricating such sys...
Patent number
8,786,080
Issue date
Jul 22, 2014
Altera Corporation
Chooi Pei Lim
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Mask set for fabricating integrated circuits and method of fabricat...
Patent number
8,758,961
Issue date
Jun 24, 2014
Altera Corporation
Jordan Plofsky
G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information
Patent Grant
Multi-layer distributed network
Patent number
8,683,405
Issue date
Mar 25, 2014
Altera Corporation
Keong Hong Oh
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Clock signal networks for structured ASIC devices
Patent number
8,595,658
Issue date
Nov 26, 2013
Altera Corporation
Chooi Pei Lim
H03 - BASIC ELECTRONIC CIRCUITRY
Information
Patent Grant
Multi-layer distributed network
Patent number
8,166,429
Issue date
Apr 24, 2012
Altera Corporation
Keong Hong Oh
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Techniques for precision biasing output driver for a calibrated on-...
Patent number
7,679,397
Issue date
Mar 16, 2010
Altera Corporation
Yew Fatt Kok
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Periphery clock signal distribution circuitry for structured ASIC d...
Patent number
7,622,952
Issue date
Nov 24, 2009
Altera Corporation
Chooi Pei Lim
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Clock signal networks for structured ASIC devices
Patent number
7,404,169
Issue date
Jul 22, 2008
Altera Corporation
Chooi Pei Lim
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
Techniques For Clock Signal Transmission In Integrated Circuits And...
Publication number
20230049681
Publication date
Feb 16, 2023
Intel Corporation
Jeffrey Chromczak
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Via Configurable Edge-Combiner with Duty Cycle Correction
Publication number
20220014182
Publication date
Jan 13, 2022
Chooi Pei Lim
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Application
Techniques For Clock Signal Transmission In Integrated Circuits And...
Publication number
20190227590
Publication date
Jul 25, 2019
Intel Corporation
Jeffrey Chromczak
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
CLOCK SYNCHRONIZATION IN MULTI-DIE FIELD PROGRAMMABLE GATE ARRAY DE...
Publication number
20190140647
Publication date
May 9, 2019
Intel Corporation
Chooi Pei Lim
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
3D BUILT-IN SELF-TEST SCHEME FOR 3D ASSEMBLY DEFECT DETECTION
Publication number
20140189456
Publication date
Jul 3, 2014
Altera Corporation
Siang Poh Loh
G01 - MEASURING TESTING
Information
Patent Application
CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES
Publication number
20140077839
Publication date
Mar 20, 2014
Altera Corporation
Chooi Pei Lim
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
SYSTEMS INCLUDING AN I/O STACK AND METHODS FOR FABRICATING SUCH SYS...
Publication number
20120228760
Publication date
Sep 13, 2012
Altera Corporation
Chooi Pei Lim
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Application
MULTI-LAYER DISTRIBUTED NETWORK
Publication number
20120169362
Publication date
Jul 5, 2012
Keong Hong Oh
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
CLOCK SIGNAL NETWORKS FOR STRUCTURED ASIC DEVICES
Publication number
20080258772
Publication date
Oct 23, 2008
Altera Corporation
Chooi Pei Lim
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Clock signal networks for structured ASIC devices
Publication number
20060267661
Publication date
Nov 30, 2006
Chooi Pei Lim
G06 - COMPUTING CALCULATING COUNTING