Choon Wei Khor

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Sungai Dua, MY

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Patents Grantslast 30 patents

Information Patent Grant
Multi-level tracking of in-use state of cache lines
- Patent number 9,348,591
- Issue date May 24, 2016
- Intel Corporation
- Ilhyun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hiding instruction cache miss latency by running tag lookups ahead...
- Patent number 9,158,696
- Issue date Oct 13, 2015
- Intel Corporation
- Ilhyun Kim
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HIDING INSTRUCTION CACHE MISS LATENCY BY RUNNING TAG LOOKUPS AHEAD...
- Publication number 20140229677
- Publication date Aug 14, 2014
- Ilhyun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL TRACKING OF IN-USE STATE OF CACHE LINES
- Publication number 20130275733
- Publication date Oct 17, 2013
- Ilhyun Kim
- G06 - COMPUTING CALCULATING COUNTING