Choong Kit Wong

Person

Penang, MY

People

Patents Grantslast 30 patents

Information Patent Grant
Dual signal protocol input/output (I/O) buffer circuit
- Patent number 10,224,911
- Issue date Mar 5, 2019
- Altera Corporation
- Tat Hin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit with an increased signal bandwidth input/output...
- Patent number 10,110,225
- Issue date Oct 23, 2018
- Altera Corporation
- Ker Yon Lau
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Packaged integrated circuit including a switch-mode regulator and m...
- Patent number 10,103,627
- Issue date Oct 16, 2018
- Altera Corporation
- Teik Wah Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for enabling and disabling transistor legs in an output...
- Patent number 9,793,888
- Issue date Oct 17, 2017
- Altera Corporation
- Tat Hin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit with configurable I/O transistor arrangement
- Patent number 8,686,758
- Issue date Apr 1, 2014
- Altera Corporation
- Ket Chiew Sia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of designing integrated circuits including providing an opti...
- Patent number 8,151,224
- Issue date Apr 3, 2012
- Altera Corporation
- Boon Jin Ang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic real-time delay characterization and configuration
- Patent number 7,787,314
- Issue date Aug 31, 2010
- Altera Corporation
- Jun Pin Tan
- G11 - INFORMATION STORAGE
Information Patent Grant
LVDS output buffer pre-emphasis methods and apparatus
- Patent number 7,265,587
- Issue date Sep 4, 2007
- Altera Corporation
- Bee Yee Ng
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low-jitter adjustable level shifter with native devices and kicker
- Patent number 7,180,329
- Issue date Feb 20, 2007
- Altera Corporation
- Ket Chiew Sia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock divider using positive and negative edge triggered state mach...
- Patent number 6,489,817
- Issue date Dec 3, 2002
- Altera Corporation
- Choong Kit Wong
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Techniques For Enabling And Disabling Transistor Legs In An Output...
- Publication number 20170264283
- Publication date Sep 14, 2017
- Altera Corporation
- Tat Hin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PACKAGED INTEGRATED CIRCUIT INCLUDING A SWITCH-MODE REGULATOR AND M...
- Publication number 20160254745
- Publication date Sep 1, 2016
- Altera Corporation
- Teik Wah Lim
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
DYNAMIC REAL-TIME DELAY CHARACTERIZATION AND CONFIGURATION
- Publication number 20100061166
- Publication date Mar 11, 2010
- Altera Corporation
- Jun Pin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY

Choong Kit Wong

Person

Patents Grantslast 30 patents

Dual signal protocol input/output (I/O) buffer circuit

Integrated circuit with an increased signal bandwidth input/output...

Packaged integrated circuit including a switch-mode regulator and m...

Techniques for enabling and disabling transistor legs in an output...

Integrated circuit with configurable I/O transistor arrangement

Method of designing integrated circuits including providing an opti...

Dynamic real-time delay characterization and configuration

LVDS output buffer pre-emphasis methods and apparatus

Low-jitter adjustable level shifter with native devices and kicker

Clock divider using positive and negative edge triggered state mach...

Patents Applicationslast 30 patents

Techniques For Enabling And Disabling Transistor Legs In An Output...

PACKAGED INTEGRATED CIRCUIT INCLUDING A SWITCH-MODE REGULATOR AND M...

DYNAMIC REAL-TIME DELAY CHARACTERIZATION AND CONFIGURATION