Chorng-Lii Hwang

Person

Wappingers Falls, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Destructive-read random access memory system buffered with destruct...
- Patent number 7,203,794
- Issue date Apr 10, 2007
- International Business Machines Corporation
- Brian L. Ji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for disconnecting a portion of an integrated circuit
- Patent number 7,057,866
- Issue date Jun 6, 2006
- International Business Machines Corp.
- Louis L. Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Destructive-read random access memory system buffered with destruct...
- Patent number 6,948,028
- Issue date Sep 20, 2005
- International Business Machines Corporation
- Brian L. Ji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Destructive-read random access memory system buffered with destruct...
- Patent number 6,801,980
- Issue date Oct 5, 2004
- International Business Machines Corporation
- Brian L. Ji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Column redundancy system and method for a micro-cell embedded DRAM...
- Patent number 6,674,673
- Issue date Jan 6, 2004
- International Business Machines Corporation
- Louis Lu-Chen Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Column redundancy system and method for a micro-cell embedded DRAM...
- Patent number 6,674,676
- Issue date Jan 6, 2004
- International Business Machines Corporation
- Louis Lu-Chen Hsu
- G11 - INFORMATION STORAGE
Information Patent Grant
Pad system for an integrated circuit or device
- Patent number 6,621,294
- Issue date Sep 16, 2003
- IBM Corporation
- Louis L. Hsu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and arrangement for preconditioning in a destructive read me...
- Patent number 6,445,611
- Issue date Sep 3, 2002
- International Business Machines Corporation
- John A. Fifield
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for resist planarization
- Patent number 6,440,638
- Issue date Aug 27, 2002
- International Business Machines Corp.
- John Golz
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method and structure for hiding a refresh operation in a DRAM havin...
- Patent number 6,404,689
- Issue date Jun 11, 2002
- International Business Machines Corporation
- Toshiaki Kirihata
- G11 - INFORMATION STORAGE
Information Patent Grant
Damascene process for forming ferroelectric capacitors
- Patent number 6,238,963
- Issue date May 29, 2001
- International Business Machines Corporation
- Bomy A. Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for reliability stressing of dielectrics
- Patent number 5,898,706
- Issue date Apr 27, 1999
- International Business Machines Corporation
- Roger Aime Dufresne
- G01 - MEASURING TESTING
Information Patent Grant
Microplanarization of rough electrodes by thin amorphous layers
- Patent number 5,587,614
- Issue date Dec 24, 1996
- Texas Instruments Incorporated
- Chorng-Lii Hwang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DESTRUCTIVE-READ RANDOM ACCESS MEMORY SYSTEM BUFFERED WITH DESTRUCT...
- Publication number 20050226083
- Publication date Oct 13, 2005
- International Business Machines Corporation
- Brian L. Ji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESTRUCTIVE-READ RANDOM ACCESS MEMORY SYSTEM BUFFERED WITH DESTRUCT...
- Publication number 20040221097
- Publication date Nov 4, 2004
- International Business Machines Corporation
- Brian L. Ji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Destructive-read random access memory system buffered with destruct...
- Publication number 20030204667
- Publication date Oct 30, 2003
- International Business Machines Corporation
- Brian L. Ji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PAD SYSTEM FOR AN INTEGRATED CIRCUIT OR DEVICE
- Publication number 20030122576
- Publication date Jul 3, 2003
- International Business Machines Corporation
- Louis L. Hsu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for disconnecting a portion of an integrated circuit
- Publication number 20030034825
- Publication date Feb 20, 2003
- International Business Machines Corporation
- Louis L. Hsu
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for background ECC scrubbing for a memory array
- Publication number 20030009721
- Publication date Jan 9, 2003
- International Business Machines Corporation
- Louis L. Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR RESIST PLANARIZATION
- Publication number 20010006761
- Publication date Jul 5, 2001
- JOHN GOLZ
- H01 - BASIC ELECTRIC ELEMENTS

Chorng-Lii Hwang

Person

Patents Grantslast 30 patents

Destructive-read random access memory system buffered with destruct...

System and method for disconnecting a portion of an integrated circuit

Destructive-read random access memory system buffered with destruct...

Destructive-read random access memory system buffered with destruct...

Column redundancy system and method for a micro-cell embedded DRAM...

Column redundancy system and method for a micro-cell embedded DRAM...

Pad system for an integrated circuit or device

Method and arrangement for preconditioning in a destructive read me...

Method and apparatus for resist planarization

Method and structure for hiding a refresh operation in a DRAM havin...

Damascene process for forming ferroelectric capacitors

Structure and method for reliability stressing of dielectrics

Microplanarization of rough electrodes by thin amorphous layers

Patents Applicationslast 30 patents

DESTRUCTIVE-READ RANDOM ACCESS MEMORY SYSTEM BUFFERED WITH DESTRUCT...

DESTRUCTIVE-READ RANDOM ACCESS MEMORY SYSTEM BUFFERED WITH DESTRUCT...

Destructive-read random access memory system buffered with destruct...

PAD SYSTEM FOR AN INTEGRATED CIRCUIT OR DEVICE

System and method for disconnecting a portion of an integrated circuit

Method and system for background ECC scrubbing for a memory array

METHOD AND APPARATUS FOR RESIST PLANARIZATION