Chris Baronne

Person

Allen, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and systems for requesting atomic operations in a computing...
- Patent number 12,197,351
- Issue date Jan 14, 2025
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread scheduling control and memory splitting in a barrel processor
- Patent number 12,135,987
- Issue date Nov 5, 2024
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parking threads in barrel processor for managing hazard clearing
- Patent number 12,099,402
- Issue date Sep 24, 2024
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rescheduling a failed memory request in a processor
- Patent number 12,020,064
- Issue date Jun 25, 2024
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-latency register error correction
- Patent number 11,953,989
- Issue date Apr 9, 2024
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parking threads in barrel processor for managing cache eviction req...
- Patent number 11,940,928
- Issue date Mar 26, 2024
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access bounds checking for a programmable atomic operator
- Patent number 11,734,173
- Issue date Aug 22, 2023
- Micron Technology, Inc.
- Tony Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bias control for a memory device
- Patent number 11,726,914
- Issue date Aug 15, 2023
- Micron Technology, Inc.
- Dean Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-demand programmable atomic kernel loading
- Patent number 11,698,791
- Issue date Jul 11, 2023
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reuse in-flight register data in a processor
- Patent number 11,614,942
- Issue date Mar 28, 2023
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread-based processor halting
- Patent number 11,586,443
- Issue date Feb 21, 2023
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-latency register error correction
- Patent number 11,507,453
- Issue date Nov 22, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bias control for a memory device
- Patent number 11,442,858
- Issue date Sep 13, 2022
- Micron Technology, Inc.
- Dean Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-demand programmable atomic kernel loading
- Patent number 11,409,539
- Issue date Aug 9, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access bounds checking for a programmable atomic operator
- Patent number 11,379,365
- Issue date Jul 5, 2022
- Micron Technology, Inc.
- Tony Brewer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PARKING THREADS IN BARREL PROCESSOR FOR MANAGING HAZARD CLEARING
- Publication number 20240419534
- Publication date Dec 19, 2024
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARKING THREADS IN BARREL PROCESSOR FOR MANAGING CACHE EVICTION REQ...
- Publication number 20240241836
- Publication date Jul 18, 2024
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARKING THREADS IN BARREL PROCESSOR FOR MANAGING HAZARD CLEARING
- Publication number 20240070011
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARKING THREADS IN BARREL PROCESSOR FOR MANAGING CACHE EVICTION REQ...
- Publication number 20240070088
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUEUEING ASYNCHRONOUS EVENTS FOR ACCEPTANCE BY THREADS EXECUTING IN...
- Publication number 20240069984
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR COMMUNICATIONS BETWEEN HARDWARE COMPONENTS
- Publication number 20240028390
- Publication date Jan 25, 2024
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR COMMUNICATIONS BETWEEN HARDWARE COMPONENTS
- Publication number 20240028206
- Publication date Jan 25, 2024
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR REQUESTING ATOMIC OPERATIONS IN A COMPUTING...
- Publication number 20240028526
- Publication date Jan 25, 2024
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC ALLOCATION OF STACK MEMORY SPACE UPON THREAD START IN A DIS...
- Publication number 20230333894
- Publication date Oct 19, 2023
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-LATENCY REGISTER ERROR CORRECTION
- Publication number 20230101219
- Publication date Mar 30, 2023
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIAS CONTROL FOR A MEMORY DEVICE
- Publication number 20230043177
- Publication date Feb 9, 2023
- Micron Technology, Inc.
- Dean Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ACCESS BOUNDS CHECKING FOR A PROGRAMMABLE ATOMIC OPERATOR
- Publication number 20220414004
- Publication date Dec 29, 2022
- Micron Technology, Inc.
- Tony Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-DEMAND PROGRAMMABLE ATOMIC KERNEL LOADING
- Publication number 20220382557
- Publication date Dec 1, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIAS CONTROL FOR A MEMORY DEVICE
- Publication number 20220292018
- Publication date Sep 15, 2022
- Micron Technology, Inc.
- Dean Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD-BASED PROCESSOR HALTING
- Publication number 20220121443
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD EXECUTION CONTROL IN A BARREL PROCESSOR
- Publication number 20220121483
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-LATENCY REGISTER ERROR CORRECTION
- Publication number 20220121516
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD REPLAY TO PRESERVE STATE IN A BARREL PROCESSOR
- Publication number 20220121485
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD SCHEDULING CONTROL AND MEMORY SPLITTING IN A BARREL PROCESSOR
- Publication number 20220121487
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESCHEDULING A FAILED MEMORY REQUEST IN A PROCESSOR
- Publication number 20220121486
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Chris Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-DEMAND PROGRAMMABLE ATOMIC KERNEL LOADING
- Publication number 20220121452
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ACCESS BOUNDS CHECKING FOR A PROGRAMMABLE ATOMIC OPERATOR
- Publication number 20220121567
- Publication date Apr 21, 2022
- Micron Technology, Inc.
- Tony Brewer
- G06 - COMPUTING CALCULATING COUNTING

Chris Baronne

Person

Patents Grantslast 30 patents

Methods and systems for requesting atomic operations in a computing...

Thread scheduling control and memory splitting in a barrel processor

Parking threads in barrel processor for managing hazard clearing

Rescheduling a failed memory request in a processor

Low-latency register error correction

Parking threads in barrel processor for managing cache eviction req...

Memory access bounds checking for a programmable atomic operator

Bias control for a memory device

On-demand programmable atomic kernel loading

Reuse in-flight register data in a processor

Thread-based processor halting

Low-latency register error correction

Bias control for a memory device

On-demand programmable atomic kernel loading

Memory access bounds checking for a programmable atomic operator

Patents Applicationslast 30 patents

PARKING THREADS IN BARREL PROCESSOR FOR MANAGING HAZARD CLEARING

PARKING THREADS IN BARREL PROCESSOR FOR MANAGING CACHE EVICTION REQ...

PARKING THREADS IN BARREL PROCESSOR FOR MANAGING HAZARD CLEARING

PARKING THREADS IN BARREL PROCESSOR FOR MANAGING CACHE EVICTION REQ...

QUEUEING ASYNCHRONOUS EVENTS FOR ACCEPTANCE BY THREADS EXECUTING IN...

METHODS AND SYSTEMS FOR COMMUNICATIONS BETWEEN HARDWARE COMPONENTS

METHODS AND SYSTEMS FOR COMMUNICATIONS BETWEEN HARDWARE COMPONENTS

METHODS AND SYSTEMS FOR REQUESTING ATOMIC OPERATIONS IN A COMPUTING...

DYNAMIC ALLOCATION OF STACK MEMORY SPACE UPON THREAD START IN A DIS...

LOW-LATENCY REGISTER ERROR CORRECTION

BIAS CONTROL FOR A MEMORY DEVICE

MEMORY ACCESS BOUNDS CHECKING FOR A PROGRAMMABLE ATOMIC OPERATOR

ON-DEMAND PROGRAMMABLE ATOMIC KERNEL LOADING

BIAS CONTROL FOR A MEMORY DEVICE

THREAD-BASED PROCESSOR HALTING

THREAD EXECUTION CONTROL IN A BARREL PROCESSOR

LOW-LATENCY REGISTER ERROR CORRECTION

THREAD REPLAY TO PRESERVE STATE IN A BARREL PROCESSOR

THREAD SCHEDULING CONTROL AND MEMORY SPLITTING IN A BARREL PROCESSOR

RESCHEDULING A FAILED MEMORY REQUEST IN A PROCESSOR

ON-DEMAND PROGRAMMABLE ATOMIC KERNEL LOADING

MEMORY ACCESS BOUNDS CHECKING FOR A PROGRAMMABLE ATOMIC OPERATOR