Chris Mozak

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Techniques for command bus training to a memory device
- Patent number 12,093,195
- Issue date Sep 17, 2024
- Intel Corporation
- Christopher P. Mozak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for duty cycle correction
- Patent number 11,916,554
- Issue date Feb 27, 2024
- Intel Corporation
- Christopher P. Mozak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for command bus training to a memory device
- Patent number 11,675,716
- Issue date Jun 13, 2023
- Intel Corporation
- Christopher P. Mozak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory command that specifies one of multiple possible write data v...
- Patent number 11,675,532
- Issue date Jun 13, 2023
- Sony Group Corporation
- Christopher E. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Applying chip select for memory device identification and power man...
- Patent number 11,335,395
- Issue date May 17, 2022
- Intel Corporation
- Christopher E. Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory command that specifies one of multiple possible write data v...
- Patent number 11,226,762
- Issue date Jan 18, 2022
- Sony Group Corporation
- Christopher E. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power gate ramp-up control apparatus and method
- Patent number 11,159,154
- Issue date Oct 26, 2021
- Intel Corporation
- Eliyah W. Kilada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DDR memory bus with a reduced data strobe signal preamble timespan
- Patent number 11,074,959
- Issue date Jul 27, 2021
- Intel Corporation
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficiently training memory device chip select control
- Patent number 11,061,590
- Issue date Jul 13, 2021
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Strong arm latch with wide common mode range
- Patent number 11,037,607
- Issue date Jun 15, 2021
- Intel Corporation
- Raymond Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual power I/O transmitter
- Patent number 10,923,164
- Issue date Feb 16, 2021
- Intel Corporation
- Hariprasath Venkatram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Applying chip select for memory device identification and power man...
- Patent number 10,839,887
- Issue date Nov 17, 2020
- Intel Corporation
- Christopher E. Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic bus inversion with programmable termination level to mainta...
- Patent number 10,802,996
- Issue date Oct 13, 2020
- Intel Corporation
- Christopher P. Mozak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic reconfigurable dual power I/O receiver
- Patent number 10,672,438
- Issue date Jun 2, 2020
- Intel Corporation
- Mohammed G. Mostofa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device, method and system for providing a delayed clock signal to a...
- Patent number 10,573,272
- Issue date Feb 25, 2020
- Intel Corporation
- Christopher Mozak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DDR memory bus with a reduced data strobe signal preamble timespan
- Patent number 10,541,018
- Issue date Jan 21, 2020
- Intel Corporation
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interference testing
- Patent number 10,516,439
- Issue date Dec 24, 2019
- Intel Corporation
- Alexey Kostinsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory subsystem I/O performance based on in-system empirical testing
- Patent number 10,446,222
- Issue date Oct 15, 2019
- Intel Corporation
- Theodore Z. Schoenborn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic bus inversion with programmable termination level to mainta...
- Patent number 10,437,746
- Issue date Oct 8, 2019
- Intel Corporation
- Christopher P. Mozak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficiently training memory device chip select control
- Patent number 10,416,912
- Issue date Sep 17, 2019
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die system electrostatic discharge protection
- Patent number 10,373,948
- Issue date Aug 6, 2019
- Intel Corporation
- Christopher P. Mozak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for dynamically adjusting voltage reference to...
- Patent number 10,347,319
- Issue date Jul 9, 2019
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Timing control for unmatched signal receiver
- Patent number 10,324,490
- Issue date Jun 18, 2019
- Intel Corporation
- Christopher P. Mozak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Row hammer refresh command
- Patent number 10,210,925
- Issue date Feb 19, 2019
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple rank high bandwidth memory
- Patent number 10,079,052
- Issue date Sep 18, 2018
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic bus inversion with programmable termination level to mainta...
- Patent number 10,031,868
- Issue date Jul 24, 2018
- Intel Corporation
- Christopher P. Mozak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple rank high bandwidth memory
- Patent number 9,934,842
- Issue date Apr 3, 2018
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Row hammer refresh command
- Patent number 9,865,326
- Issue date Jan 9, 2018
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Lower-power scrambling with improved signal integrity
- Patent number 9,792,246
- Issue date Oct 17, 2017
- Intel Corporation
- Ee Loon Teoh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Row hammer refresh command
- Patent number 9,747,971
- Issue date Aug 29, 2017
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE
- Publication number 20240370390
- Publication date Nov 7, 2024
- Intel Corporation
- Christopher P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODULAR MEMORY BLOCKS FOR INTEGRATED CIRCUIT DEVICES
- Publication number 20240222347
- Publication date Jul 4, 2024
- Intel Corporation
- Sagar Suthram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES FOR DUTY CYCLE CORRECTION
- Publication number 20240113700
- Publication date Apr 4, 2024
- Intel Corporation
- Christopher P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE
- Publication number 20230297523
- Publication date Sep 21, 2023
- Intel Corporation
- Christopher P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE ECC MODE IN DRAM
- Publication number 20230223096
- Publication date Jul 13, 2023
- Intel Corporation
- Kuljit S. BAINS
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CHIP STACK FOR HIGH PERFORMANCE LOGIC CHIPS
- Publication number 20230125041
- Publication date Apr 20, 2023
- Intel Corporation
- Christopher P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIDIRECTIONAL COMMAND BUS PHASE DRIFT COMPENSATION
- Publication number 20220393682
- Publication date Dec 8, 2022
- Intel Corporation
- James A. McCALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULL DUPLEX DRAM FOR TIGHTLY COUPLED COMPUTE DIE AND MEMORY DIE
- Publication number 20220392519
- Publication date Dec 8, 2022
- Intel Corporation
- Randy B. OSBORNE
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY COMMAND THAT SPECIFIES ONE OF MULTIPLE POSSIBLE WRITE DATA V...
- Publication number 20220121392
- Publication date Apr 21, 2022
- SONY GROUP CORPORATION
- Christopher E. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST SELF-REFRESH EXIT POWER STATE
- Publication number 20220121263
- Publication date Apr 21, 2022
- Intel Corporation
- Christopher P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD TO INCREASE EFFECTIVE CAPACITANCE WITH LAYOUT...
- Publication number 20210167014
- Publication date Jun 3, 2021
- Intel Corporation
- Kushal Sreedhar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...
- Publication number 20210020224
- Publication date Jan 21, 2021
- Intel Corporation
- Christopher E. COX
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSMIT CROSSTALK CANCELLATION SYSTEM
- Publication number 20200313722
- Publication date Oct 1, 2020
- Intel Corporation
- James Alexander McCall
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DDR MEMORY BUS WITH A REDUCED DATA STROBE SIGNAL PREAMBLE TIMESPAN
- Publication number 20200286543
- Publication date Sep 10, 2020
- Intel Corporation
- James A. McCALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRONG ARM LATCH WITH WIDE COMMON MODE RANGE
- Publication number 20200194039
- Publication date Jun 18, 2020
- Intel Corporation
- Raymond CHONG
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TECHNIQUES FOR DUTY CYCLE CORRECTION
- Publication number 20200119721
- Publication date Apr 16, 2020
- Intel Corporation
- Christopher P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENTLY TRAINING MEMORY DEVICE CHIP SELECT CONTROL
- Publication number 20200110551
- Publication date Apr 9, 2020
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE
- Publication number 20200110716
- Publication date Apr 9, 2020
- Intel Corporation
- Christopher P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL POWER I/O TRANSMITTER
- Publication number 20200105317
- Publication date Apr 2, 2020
- Intel Corporation
- Hariprasath VENKATRAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RECONFIGURABLE DUAL POWER I/O RECEIVER
- Publication number 20200105319
- Publication date Apr 2, 2020
- Intel Corporation
- Mohammed G. Mostofa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC BUS INVERSION WITH PROGRAMMABLE TERMINATION LEVEL TO MAINTA...
- Publication number 20200081852
- Publication date Mar 12, 2020
- Intel Corporation
- Christopher P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE, METHOD AND SYSTEM FOR PROVIDING A DELAYED CLOCK SIGNAL TO A...
- Publication number 20200005729
- Publication date Jan 2, 2020
- Intel Corporation
- Christopher Mozak
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Application
APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...
- Publication number 20190392886
- Publication date Dec 26, 2019
- Intel Corporation
- Christopher E. COX
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY COMMAND THAT SPECIFIES ONE OF MULTIPLE POSSIBLE WRITE DATA V...
- Publication number 20190163393
- Publication date May 30, 2019
- Intel Corporation
- Christopher E. COX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC BUS INVERSION WITH PROGRAMMABLE TERMINATION LEVEL TO MAINTA...
- Publication number 20190121754
- Publication date Apr 25, 2019
- Intel Corporation
- Christopher P. MOZAK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DDR MEMORY BUS WITH A REDUCED DATA STROBE SIGNAL PREAMBLE TIMESPAN
- Publication number 20190096468
- Publication date Mar 28, 2019
- James A. McCALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER GATE RAMP-UP CONTROL APPARATUS AND METHOD
- Publication number 20180278246
- Publication date Sep 27, 2018
- Eliyah W. KILADA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE RANK HIGH BANDWIDTH MEMORY
- Publication number 20180226118
- Publication date Aug 9, 2018
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR TRAINING ONE OR MORE SIGNAL TIMING RELA...
- Publication number 20180181504
- Publication date Jun 28, 2018
- Intel Corporation
- Tonia Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROW HAMMER REFRESH COMMAND
- Publication number 20180174639
- Publication date Jun 21, 2018
- Intel Corporation
- Kuljit S Bains
- G06 - COMPUTING CALCULATING COUNTING

Chris Mozak

Person

Patents Grantslast 30 patents

Techniques for command bus training to a memory device

Techniques for duty cycle correction

Techniques for command bus training to a memory device

Memory command that specifies one of multiple possible write data v...

Applying chip select for memory device identification and power man...

Memory command that specifies one of multiple possible write data v...

Power gate ramp-up control apparatus and method

DDR memory bus with a reduced data strobe signal preamble timespan

Efficiently training memory device chip select control

Strong arm latch with wide common mode range

Dual power I/O transmitter

Applying chip select for memory device identification and power man...

Dynamic bus inversion with programmable termination level to mainta...

Dynamic reconfigurable dual power I/O receiver

Device, method and system for providing a delayed clock signal to a...

DDR memory bus with a reduced data strobe signal preamble timespan

Interference testing

Memory subsystem I/O performance based on in-system empirical testing

Dynamic bus inversion with programmable termination level to mainta...

Efficiently training memory device chip select control

On-die system electrostatic discharge protection

Method and apparatus for dynamically adjusting voltage reference to...

Timing control for unmatched signal receiver

Row hammer refresh command

Multiple rank high bandwidth memory

Dynamic bus inversion with programmable termination level to mainta...

Multiple rank high bandwidth memory

Row hammer refresh command

Lower-power scrambling with improved signal integrity

Row hammer refresh command

Patents Applicationslast 30 patents

TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE

MODULAR MEMORY BLOCKS FOR INTEGRATED CIRCUIT DEVICES

TECHNIQUES FOR DUTY CYCLE CORRECTION

TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE

CONFIGURABLE ECC MODE IN DRAM

MEMORY CHIP STACK FOR HIGH PERFORMANCE LOGIC CHIPS

UNIDIRECTIONAL COMMAND BUS PHASE DRIFT COMPENSATION

FULL DUPLEX DRAM FOR TIGHTLY COUPLED COMPUTE DIE AND MEMORY DIE

MEMORY COMMAND THAT SPECIFIES ONE OF MULTIPLE POSSIBLE WRITE DATA V...

FAST SELF-REFRESH EXIT POWER STATE

APPARATUS AND METHOD TO INCREASE EFFECTIVE CAPACITANCE WITH LAYOUT...

APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...

TRANSMIT CROSSTALK CANCELLATION SYSTEM

DDR MEMORY BUS WITH A REDUCED DATA STROBE SIGNAL PREAMBLE TIMESPAN

STRONG ARM LATCH WITH WIDE COMMON MODE RANGE

TECHNIQUES FOR DUTY CYCLE CORRECTION

EFFICIENTLY TRAINING MEMORY DEVICE CHIP SELECT CONTROL

TECHNIQUES FOR COMMAND BUS TRAINING TO A MEMORY DEVICE

DUAL POWER I/O TRANSMITTER

DYNAMIC RECONFIGURABLE DUAL POWER I/O RECEIVER

DYNAMIC BUS INVERSION WITH PROGRAMMABLE TERMINATION LEVEL TO MAINTA...

DEVICE, METHOD AND SYSTEM FOR PROVIDING A DELAYED CLOCK SIGNAL TO A...

APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...

MEMORY COMMAND THAT SPECIFIES ONE OF MULTIPLE POSSIBLE WRITE DATA V...

DYNAMIC BUS INVERSION WITH PROGRAMMABLE TERMINATION LEVEL TO MAINTA...

DDR MEMORY BUS WITH A REDUCED DATA STROBE SIGNAL PREAMBLE TIMESPAN

POWER GATE RAMP-UP CONTROL APPARATUS AND METHOD

MULTIPLE RANK HIGH BANDWIDTH MEMORY

APPARATUSES AND METHODS FOR TRAINING ONE OR MORE SIGNAL TIMING RELA...

ROW HAMMER REFRESH COMMAND