Christian Weis

Person

Munich, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Memory chip with settable termination resistance circuit
- Patent number 7,532,523
- Issue date May 12, 2009
- Qimonda AG
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory and method for adapting the phase relationship...
- Patent number 7,457,174
- Issue date Nov 25, 2008
- Infineon Technologies AG
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay locked loop
- Patent number 7,457,392
- Issue date Nov 25, 2008
- Infineon Technologies AG
- Christian Weis
- G11 - INFORMATION STORAGE
Information Patent Grant
Device in a memory circuit for definition of waiting times
- Patent number 7,355,921
- Issue date Apr 8, 2008
- Infineon Technologies AG
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit arrangement for controlling write access to a se...
- Patent number 7,224,625
- Issue date May 29, 2007
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and device for data transfer
- Patent number 7,120,818
- Issue date Oct 10, 2006
- Infineon Technologies AG
- Stefan Dietrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated memory, and a method of operating an integrated memory
- Patent number 6,882,554
- Issue date Apr 19, 2005
- Infineon Technologies AG
- Michael Markert
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit and method for operating the integrated circuit
- Patent number 6,847,581
- Issue date Jan 25, 2005
- Infineon Technologies AG
- Pramod Acharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Control circuit for an S-DRAM
- Patent number 6,717,886
- Issue date Apr 6, 2004
- Infineon Technologies AG
- Acharya Pramod
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having a test operating mode and method for test...
- Patent number 6,670,802
- Issue date Dec 30, 2003
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration with a memory array
- Patent number 6,614,700
- Issue date Sep 2, 2003
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage pump with switch-on control
- Patent number 6,542,389
- Issue date Apr 1, 2003
- Infineon Technology AG
- Stefan Dietrich
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Integrated memory having a row access controller for activating and...
- Patent number 6,532,188
- Issue date Mar 11, 2003
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for programming a delay in a signal path
- Patent number 6,480,024
- Issue date Nov 12, 2002
- Infineon Technologies AG
- Stefan Dietrich
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated memory
- Patent number 6,437,410
- Issue date Aug 20, 2002
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having a command decoder
- Patent number 6,404,699
- Issue date Jun 11, 2002
- Infineon Technologies AG
- Peter Schrögmeier
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory with row access control to activate and precharge...
- Patent number 6,396,755
- Issue date May 28, 2002
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having a decoder unit and an additional input of...
- Patent number 6,385,123
- Issue date May 7, 2002
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit configuration for read-write mode control of a s...
- Patent number 6,359,832
- Issue date Mar 19, 2002
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory with a block writing function and global amplifie...
- Patent number 6,351,419
- Issue date Feb 26, 2002
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory with two burst operation types
- Patent number 6,310,824
- Issue date Oct 30, 2001
- Infineon Technologies AG
- Sabine Schöniger
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory having redundant units of memory cells, and test...
- Patent number 6,285,605
- Issue date Sep 4, 2001
- Infineon Technologies AG
- Peter Schrögmeier
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous integrated memory
- Patent number 6,275,445
- Issue date Aug 14, 2001
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory
- Patent number 6,272,035
- Issue date Aug 7, 2001
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory having memory cells disposed at crossover points...
- Patent number 6,256,219
- Issue date Jul 3, 2001
- Infineon Technologies AG
- Peter Schrögmeier
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY CHIP AND METHOD FOR OPERATING A MEMORY CHIP
- Publication number 20070035326
- Publication date Feb 15, 2007
- Georg Braun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor memory and method for adapting the phase relationship...
- Publication number 20060262613
- Publication date Nov 23, 2006
- Georg Braun
- G11 - INFORMATION STORAGE
Information Patent Application
Device in a memory circuit for definition of waiting times
- Publication number 20060233005
- Publication date Oct 19, 2006
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Application
Method and circuit arrangement for controlling write access to a se...
- Publication number 20050254307
- Publication date Nov 17, 2005
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Control circuit for an S-DRAM
- Publication number 20030161210
- Publication date Aug 28, 2003
- Pramod Acharya
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit and method for operating the integrated circuit
- Publication number 20030132792
- Publication date Jul 17, 2003
- Pramod Acharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrated circuit and method for operating a test configuration wi...
- Publication number 20030135795
- Publication date Jul 17, 2003
- Christian Weis
- G01 - MEASURING TESTING
Information Patent Application
Integrated memory, and a method of operating an integrated memory
- Publication number 20030107910
- Publication date Jun 12, 2003
- Michael Markert
- G11 - INFORMATION STORAGE
Information Patent Application
Delay locked loop
- Publication number 20030094984
- Publication date May 22, 2003
- Christian Weis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuit configuration with a memory array
- Publication number 20020145923
- Publication date Oct 10, 2002
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory having a row access controller for activating and...
- Publication number 20020141279
- Publication date Oct 3, 2002
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Method and device for data transfer
- Publication number 20020136243
- Publication date Sep 26, 2002
- Stefan Dietrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit having a test operating mode and method for test...
- Publication number 20020133750
- Publication date Sep 19, 2002
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit configuration for programming a delay in a signal path
- Publication number 20020079925
- Publication date Jun 27, 2002
- Stefan Dietrich
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Voltage pump with switch-on control
- Publication number 20020075707
- Publication date Jun 20, 2002
- Stefan Dietrich
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
Integrated memory with row access control to activate and precharge...
- Publication number 20010046172
- Publication date Nov 29, 2001
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Method and circuit configuration for read-write mode control of a s...
- Publication number 20010043503
- Publication date Nov 22, 2001
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Memory configuration having a circuit for determining the activated...
- Publication number 20010026498
- Publication date Oct 4, 2001
- Stefan Dietrich
- G11 - INFORMATION STORAGE

Christian Weis

Person

Patents Grantslast 30 patents

Memory chip with settable termination resistance circuit

Semiconductor memory and method for adapting the phase relationship...

Delay locked loop

Device in a memory circuit for definition of waiting times

Method and circuit arrangement for controlling write access to a se...

Method and device for data transfer

Integrated memory, and a method of operating an integrated memory

Integrated circuit and method for operating the integrated circuit

Control circuit for an S-DRAM

Integrated circuit having a test operating mode and method for test...

Circuit configuration with a memory array

Voltage pump with switch-on control

Integrated memory having a row access controller for activating and...

Circuit configuration for programming a delay in a signal path

Integrated memory

Integrated circuit having a command decoder

Integrated memory with row access control to activate and precharge...

Integrated circuit having a decoder unit and an additional input of...

Method and circuit configuration for read-write mode control of a s...

Integrated memory with a block writing function and global amplifie...

Integrated memory with two burst operation types

Integrated memory having redundant units of memory cells, and test...

Synchronous integrated memory

Integrated memory

Integrated memory having memory cells disposed at crossover points...

Patents Applicationslast 30 patents

MEMORY CHIP AND METHOD FOR OPERATING A MEMORY CHIP

Semiconductor memory and method for adapting the phase relationship...

Device in a memory circuit for definition of waiting times

Method and circuit arrangement for controlling write access to a se...

Control circuit for an S-DRAM

Integrated circuit and method for operating the integrated circuit

Integrated circuit and method for operating a test configuration wi...

Integrated memory, and a method of operating an integrated memory

Delay locked loop

Circuit configuration with a memory array

Integrated memory having a row access controller for activating and...

Method and device for data transfer

Integrated circuit having a test operating mode and method for test...

Circuit configuration for programming a delay in a signal path

Voltage pump with switch-on control

Integrated memory with row access control to activate and precharge...

Method and circuit configuration for read-write mode control of a s...

Memory configuration having a circuit for determining the activated...