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Christoph ALBRECHT
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Berkeley, CA, US
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Patents Grants
last 30 patents
Information
Patent Grant
Methods for designing intergrated circuits with automatically synth...
Patent number
8,887,110
Issue date
Nov 11, 2014
Cadence Design Systems, Inc.
Radu Zlatanovici
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Optimizing integrated circuit design through use of sequential timi...
Patent number
8,589,845
Issue date
Nov 19, 2013
Christoph Albrecht
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Reducing critical cycle delay in an integrated circuit design throu...
Patent number
8,307,316
Issue date
Nov 6, 2012
Cadence Design Systems, Inc.
Christoph Albrecht
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Automatic synthesis of clock distribution networks
Patent number
8,205,182
Issue date
Jun 19, 2012
Cadence Design Systems, Inc.
Radu Zlatanovici
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Constraint based retiming of synchronous circuits
Patent number
7,945,880
Issue date
May 17, 2011
Cadence Design Systems, Inc.
Christoph Albrecht
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Reducing critical cycle delay in an integrated circuit design throu...
Patent number
7,913,210
Issue date
Mar 22, 2011
Cadence Design Systems, Inc.
Christoph Albrecht
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Optimizing integrated circuit design through use of sequential timi...
Patent number
7,743,354
Issue date
Jun 22, 2010
Cadence Design Systems, Inc.
Christoph Albrecht
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Optimizing integrated circuit design through balanced combinational...
Patent number
7,739,642
Issue date
Jun 15, 2010
Cadence Design Systems, Inc.
Christoph Albrecht
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Data path and placement optimization in an integrated circuit throu...
Patent number
7,624,364
Issue date
Nov 24, 2009
Cadence Design Systems, Inc.
Christoph Albrecht
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Optimization of combinational logic synthesis through clock latency...
Patent number
7,559,040
Issue date
Jul 7, 2009
Cadence Design Systems, Inc.
Christoph Albrecht
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Floorplan evaluation, global routing, and buffer insertion for inte...
Patent number
7,062,743
Issue date
Jun 13, 2006
The Regents of the University of California
Andrew B. Kahng
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
REDUCING CRITICAL CYCLE DELAY IN AN INTEGRATED CIRCUIT DESIGN THROU...
Publication number
20110252389
Publication date
Oct 13, 2011
Cadence Design Systems, Inc.
Christoph ALBRECHT
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
OPTIMIZING INTEGRATED CIRCUIT DESIGN THROUGH USE OF SEQUENTIAL TIMI...
Publication number
20100115477
Publication date
May 6, 2010
Cadence Design Systems, Inc.
Christoph ALBRECHT
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Optimizing integrated circuit design through use of sequential timi...
Publication number
20080276210
Publication date
Nov 6, 2008
Christoph Albrecht
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
OPTIMIZING INTEGRATED CIRCUIT DESIGN THROUGH USE OF SEQUENTIAL TIMI...
Publication number
20080276208
Publication date
Nov 6, 2008
Christoph Albrecht
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Optimizing integrated circuit design through use of sequential timi...
Publication number
20080276209
Publication date
Nov 6, 2008
Christoph Albrecht
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Floorplan evaluation, global routing, and buffer insertion for inte...
Publication number
20040117753
Publication date
Jun 17, 2004
The Regents of the University of California.
Andrew B. Kahng
G06 - COMPUTING CALCULATING COUNTING