Christoph Jaeschke

Person

Tuebingen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor chip with a plurality of scannable storage elements a...
- Patent number 7,996,738
- Issue date Aug 9, 2011
- International Business Machines Corporation
- Tobias Gemmeke
- G01 - MEASURING TESTING
Information Patent Grant
Driving values to DC adjusted/untimed nets to identify timing problems
- Patent number 7,886,244
- Issue date Feb 8, 2011
- International Business Machines Corporation
- Robert B. Gass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for performing verification of logic circuits
- Patent number 7,565,636
- Issue date Jul 21, 2009
- International Business Machines Corporation
- Bodo Hoppe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for driving values to DC adjusted/untimed nets to identify t...
- Patent number 7,490,305
- Issue date Feb 10, 2009
- International Business Machines Corporation
- Robert B. Gass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for performing verification of logic circuits
- Patent number 7,398,494
- Issue date Jul 8, 2008
- International Business Machines Corporation
- Bodo Hoppe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for verification of gate level netlists using colored bits
- Patent number 7,213,220
- Issue date May 1, 2007
- International Business Machines Corporation
- Bodo Hoppe
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LARGE SCALE FORMAL ANALYSIS BY STRUCTURAL PREPROCESSING
- Publication number 20120151423
- Publication date Jun 14, 2012
- International Business Machines Corporation
- Jason R. Baumgartner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR PERFORMING LOGIC BUILT-IN-SELF-TEST CYCLES ON A SEMICOND...
- Publication number 20090228751
- Publication date Sep 10, 2009
- Tilman Gloekler
- G01 - MEASURING TESTING
Information Patent Application
Driving Values to DC Adjusted/Untimed Nets to Identify Timing Problems
- Publication number 20090132983
- Publication date May 21, 2009
- International Business Machines Corporation
- Robert B. Gass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR CHIP WITH A PLURALITY OF SCANNABLE STORAGE ELEMENTS A...
- Publication number 20080276140
- Publication date Nov 6, 2008
- Tobias Gemmeke
- G01 - MEASURING TESTING
Information Patent Application
System for Performing Verification of Logic Circuits
- Publication number 20080216030
- Publication date Sep 4, 2008
- International Business Machines Corporation
- Bodo Hoppe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Driving Values to DC Adjusted/Untimed Nets to...
- Publication number 20080016480
- Publication date Jan 17, 2008
- Robert B. Gass
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Performing Verification of Logic Circuits
- Publication number 20070050739
- Publication date Mar 1, 2007
- Bodo Hoppe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for verification of gate level netlisits using colored bits
- Publication number 20050138586
- Publication date Jun 23, 2005
- International Business Machines Corporation
- Bodo Hoppe
- G06 - COMPUTING CALCULATING COUNTING

Christoph Jaeschke

Person

Patents Grantslast 30 patents

Semiconductor chip with a plurality of scannable storage elements a...

Driving values to DC adjusted/untimed nets to identify timing problems

System for performing verification of logic circuits

Method for driving values to DC adjusted/untimed nets to identify t...

Method for performing verification of logic circuits

Method for verification of gate level netlists using colored bits

Patents Applicationslast 30 patents

LARGE SCALE FORMAL ANALYSIS BY STRUCTURAL PREPROCESSING

METHOD FOR PERFORMING LOGIC BUILT-IN-SELF-TEST CYCLES ON A SEMICOND...

Driving Values to DC Adjusted/Untimed Nets to Identify Timing Problems

SEMICONDUCTOR CHIP WITH A PLURALITY OF SCANNABLE STORAGE ELEMENTS A...

System for Performing Verification of Logic Circuits

System and Method for Driving Values to DC Adjusted/Untimed Nets to...

Method and System for Performing Verification of Logic Circuits

Method for verification of gate level netlisits using colored bits