Christophe Figuet

Person

Fontaine, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Carrier for a semiconductor structure
- Patent number 11,251,265
- Issue date Feb 15, 2022
- Soitec
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a structure for forming a tridimensional m...
- Patent number 11,205,702
- Issue date Dec 21, 2021
- Soitec
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure for radiofrequency applications
- Patent number 10,250,282
- Issue date Apr 2, 2019
- Soitec
- Oleg Kononchuk
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method for separating at least two substrates along a selected inte...
- Patent number 10,093,086
- Issue date Oct 9, 2018
- Soitec
- Didier Landru
- B32 - LAYERED PRODUCTS
Information Patent Grant
Method for transferring a layer of a semiconductor and substrate co...
- Patent number 9,716,029
- Issue date Jul 25, 2017
- Soitec
- Fabrice Lallement
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a composite structure to be separated by exf...
- Patent number 9,646,825
- Issue date May 9, 2017
- Soitec
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for separating at least two substrates along a selected inte...
- Patent number 9,437,473
- Issue date Sep 6, 2016
- Soitec
- Didier Landru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structures including stacks of indium gallium nitride...
- Patent number 9,276,070
- Issue date Mar 1, 2016
- Soitec
- Christophe Figuet
- C30 - CRYSTAL GROWTH
Information Patent Grant
Electronic device for radiofrequency or power applications and proc...
- Patent number 9,198,294
- Issue date Nov 24, 2015
- Soitec
- Didier Landru
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
III-V semiconductor structures with diminished pit defects and meth...
- Patent number 8,975,165
- Issue date Mar 10, 2015
- Soitec
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deposition methods for the formation of III/V semiconductor materia...
- Patent number 8,742,428
- Issue date Jun 3, 2014
- Soitec
- Christophe Figuet
- C30 - CRYSTAL GROWTH
Information Patent Grant
Method for fabricating a semiconductor substrate
- Patent number 8,575,010
- Issue date Nov 5, 2013
- Soitec
- Alexis Drouin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deposition methods for the formation of III/V semiconductor materia...
- Patent number 8,329,571
- Issue date Dec 11, 2012
- Soitec
- Christophe Figuet
- C30 - CRYSTAL GROWTH
Information Patent Grant
(110) oriented silicon substrate and a bonded pair of substrates co...
- Patent number 8,309,437
- Issue date Nov 13, 2012
- Soitec
- Christophe Figuet
- C30 - CRYSTAL GROWTH
Information Patent Grant
Methods of forming III/V semiconductor materials, and semiconductor...
- Patent number 8,148,252
- Issue date Apr 3, 2012
- S.O.I. Tec Silicon on Insulator Technologies
- Christophe Figuet
- C30 - CRYSTAL GROWTH
Information Patent Grant
Semiconductor heterostructure and method for forming same
- Patent number 8,084,784
- Issue date Dec 27, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained layers within semiconductor buffer structures
- Patent number 7,825,401
- Issue date Nov 2, 2010
- ASM America, Inc.
- Nyles W. Cody
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor heterostructure and method for forming same
- Patent number 7,772,127
- Issue date Aug 10, 2010
- S.O.I. Tec Silicon on Insulator Technologies
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained layers within semiconductor buffer structures
- Patent number 7,608,526
- Issue date Oct 27, 2009
- ASM America, Inc.
- Nyles W. Cody
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor heterostructure
- Patent number 7,544,976
- Issue date Jun 9, 2009
- S.O.I. Tec Silicon on Insulator Technologies
- Cécile Aulnette
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor heterostructure
- Patent number 7,459,374
- Issue date Dec 2, 2008
- S.O.I. Tec Silicon on Insulator Technologies
- Cécile Aulnette
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Laminated layer structure and method for forming the same
- Patent number 7,387,953
- Issue date Jun 17, 2008
- S.O.I. Tec Silicon on Insulator Technologies
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for selectively transferring at least an element from an ini...
- Patent number 6,959,863
- Issue date Nov 1, 2005
- Commissariat a l'Engergie Atomique
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR STRUCTURE FOR OPTOELECTRONIC APPLICATIONS
- Publication number 20240429683
- Publication date Dec 26, 2024
- SOITEC
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING A STRUCTURE FOR FORMING A TRIDIMENSIONAL M...
- Publication number 20200295138
- Publication date Sep 17, 2020
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CARRIER FOR A SEMICONDUCTOR STRUCTURE
- Publication number 20190058031
- Publication date Feb 21, 2019
- SOITEC
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE FOR RADIOFREQUENCY APPLICATIONS
- Publication number 20170331501
- Publication date Nov 16, 2017
- SOITEC
- Oleg Kononchuk
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR SEPARATING AT LEAST TWO SUBSTRATES ALONG A SELECTED INTE...
- Publication number 20160368259
- Publication date Dec 22, 2016
- SOITEC
- Didier Landru
- B32 - LAYERED PRODUCTS
Information Patent Application
METHOD FOR SEPARATING AT LEAST TWO SUBSTRATES ALONG A SELECTED INTE...
- Publication number 20150221544
- Publication date Aug 6, 2015
- SOITEC
- Didier Landru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A COMPOSITE STRUCTURE TO BE SEPARATED BY EXF...
- Publication number 20140339681
- Publication date Nov 20, 2014
- SOITEC
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURES INCLUDING STACKS OF INDIUM GALLIUM NITRIDE...
- Publication number 20140217419
- Publication date Aug 7, 2014
- SOITEC
- Christophe Figuet
- C30 - CRYSTAL GROWTH
Information Patent Application
METHOD FOR TRANSFERRING A LAYER OF A SEMICONDUCTOR AND SUBSTRATE CO...
- Publication number 20140183601
- Publication date Jul 3, 2014
- SOITEC
- Fabrice Lallement
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
QUANTUM WELL THERMOELECTRIC COMPONENT FOR USE IN A THERMOELECTRIC D...
- Publication number 20140027714
- Publication date Jan 30, 2014
- SOITEC
- Daniel Delprat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE FOR RADIOFREQUENCY OR POWER APPLICATIONS AND PROC...
- Publication number 20130294038
- Publication date Nov 7, 2013
- SOITEC
- Didier Landru
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEPOSITION METHODS FOR THE FORMATION OF III/V SEMICONDUCTOR MATERIA...
- Publication number 20130049012
- Publication date Feb 28, 2013
- SOITEC
- Christophe Figuet
- C30 - CRYSTAL GROWTH
Information Patent Application
DEPOSITION METHODS FOR THE FORMATION OF III/V SEMICONDUCTOR MATERIA...
- Publication number 20120225539
- Publication date Sep 6, 2012
- SOITEC
- Christophe Figuet
- C30 - CRYSTAL GROWTH
Information Patent Application
III-V SEMICONDUCTOR STRUCTURES WITH DIMINISHED PIT DEFECTS AND METH...
- Publication number 20120211870
- Publication date Aug 23, 2012
- S.O.I TEC SILICON ON INSULATOR TECHNOLOGIES
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER...
- Publication number 20110183493
- Publication date Jul 28, 2011
- S.O.I TEC SILICON ON INSULATOR TECHNOLOGIES
- Nicolas Daval
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A SEMICONDUCTOR SUBSTRATE
- Publication number 20110024868
- Publication date Feb 3, 2011
- Alexis Drouin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR HETEROSTRUCTURE AND METHOD FOR FORMING SAME
- Publication number 20100264463
- Publication date Oct 21, 2010
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR...
- Publication number 20100164048
- Publication date Jul 1, 2010
- S. O. I. Tec Silicon on Insulator Technologies
- Christophe Figuet
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
(110) ORIENTED SILICON SUBSTRATE AND A BONDED PAIR OF SUBSTRATES CO...
- Publication number 20100038756
- Publication date Feb 18, 2010
- S. O. I. Tec Silicon on Insulator Technologies
- Christophe Figuet
- C30 - CRYSTAL GROWTH
Information Patent Application
STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES
- Publication number 20100006893
- Publication date Jan 14, 2010
- ASM AMERICA, INC
- Nyles W. Cody
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Strained layers within semiconductor buffer structures
- Publication number 20080017952
- Publication date Jan 24, 2008
- ASM America, Inc.
- Nyles W. Cody
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor heterostructure and method for forming same
- Publication number 20070051975
- Publication date Mar 8, 2007
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Laminated layer structure and method for forming the same
- Publication number 20060211230
- Publication date Sep 21, 2006
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for selectively transferring at least an element from an ini...
- Publication number 20040104272
- Publication date Jun 3, 2004
- Christophe Figuet
- H01 - BASIC ELECTRIC ELEMENTS

Christophe Figuet

Person

Patents Grantslast 30 patents

Carrier for a semiconductor structure

Method for manufacturing a structure for forming a tridimensional m...

Structure for radiofrequency applications

Method for separating at least two substrates along a selected inte...

Method for transferring a layer of a semiconductor and substrate co...

Method for fabricating a composite structure to be separated by exf...

Method for separating at least two substrates along a selected inte...

Semiconductor structures including stacks of indium gallium nitride...

Electronic device for radiofrequency or power applications and proc...

III-V semiconductor structures with diminished pit defects and meth...

Deposition methods for the formation of III/V semiconductor materia...

Method for fabricating a semiconductor substrate

Deposition methods for the formation of III/V semiconductor materia...

(110) oriented silicon substrate and a bonded pair of substrates co...

Methods of forming III/V semiconductor materials, and semiconductor...

Semiconductor heterostructure and method for forming same

Strained layers within semiconductor buffer structures

Semiconductor heterostructure and method for forming same

Strained layers within semiconductor buffer structures

Semiconductor heterostructure

Method of manufacturing a semiconductor heterostructure

Laminated layer structure and method for forming the same

Method for selectively transferring at least an element from an ini...

Patents Applicationslast 30 patents

SEMICONDUCTOR STRUCTURE FOR OPTOELECTRONIC APPLICATIONS

METHOD FOR MANUFACTURING A STRUCTURE FOR FORMING A TRIDIMENSIONAL M...

CARRIER FOR A SEMICONDUCTOR STRUCTURE

STRUCTURE FOR RADIOFREQUENCY APPLICATIONS

METHOD FOR SEPARATING AT LEAST TWO SUBSTRATES ALONG A SELECTED INTE...

METHOD FOR SEPARATING AT LEAST TWO SUBSTRATES ALONG A SELECTED INTE...

METHOD FOR FABRICATING A COMPOSITE STRUCTURE TO BE SEPARATED BY EXF...

SEMICONDUCTOR STRUCTURES INCLUDING STACKS OF INDIUM GALLIUM NITRIDE...

METHOD FOR TRANSFERRING A LAYER OF A SEMICONDUCTOR AND SUBSTRATE CO...

QUANTUM WELL THERMOELECTRIC COMPONENT FOR USE IN A THERMOELECTRIC D...

ELECTRONIC DEVICE FOR RADIOFREQUENCY OR POWER APPLICATIONS AND PROC...

DEPOSITION METHODS FOR THE FORMATION OF III/V SEMICONDUCTOR MATERIA...

DEPOSITION METHODS FOR THE FORMATION OF III/V SEMICONDUCTOR MATERIA...

III-V SEMICONDUCTOR STRUCTURES WITH DIMINISHED PIT DEFECTS AND METH...

PROCESS FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER...

METHOD FOR FABRICATING A SEMICONDUCTOR SUBSTRATE

SEMICONDUCTOR HETEROSTRUCTURE AND METHOD FOR FORMING SAME

METHOD FOR FABRICATING A SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR...

(110) ORIENTED SILICON SUBSTRATE AND A BONDED PAIR OF SUBSTRATES CO...

STRAINED LAYERS WITHIN SEMICONDUCTOR BUFFER STRUCTURES

Strained layers within semiconductor buffer structures

Semiconductor heterostructure and method for forming same

Laminated layer structure and method for forming the same

Method for selectively transferring at least an element from an ini...