Christophe Laurent

Person

Agrate Brianza (MI), IT

People

Patents Grantslast 30 patents

Information Patent Grant
Balanced codewords for reducing a selected state in memory cells
- Patent number 12,321,610
- Issue date Jun 3, 2025
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel access in a memory array
- Patent number 12,300,305
- Issue date May 13, 2025
- Micron Technology, Inc.
- Efrem Bolandrina
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having an improved ECC architecture
- Patent number 12,288,591
- Issue date Apr 29, 2025
- Micron Technology, Inc.
- Christophe Laurent
- G11 - INFORMATION STORAGE
Information Patent Grant
Performing sense operations in memory
- Patent number 12,288,592
- Issue date Apr 29, 2025
- Micron Technology, Inc.
- Michele Maria Venturini
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems for improving ECC operation of memories
- Patent number 12,266,410
- Issue date Apr 1, 2025
- Micron Technology, Inc.
- Christophe Laurent
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared decoder architecture for three-dimensional memory arrays
- Patent number 12,260,907
- Issue date Mar 25, 2025
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture-based power management for a memory device
- Patent number 12,228,991
- Issue date Feb 18, 2025
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit partitioning for a memory device
- Patent number 12,182,432
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- Andrea Martinelli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ECC configuration in memories
- Patent number 12,135,610
- Issue date Nov 5, 2024
- Micron Technology, Inc.
- Graziano Mirichigni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with data scrubbing capability and methods
- Patent number 12,086,421
- Issue date Sep 10, 2024
- Micron Technology, Inc.
- Graziano Mirichigni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for managing memory with dynamic ECC protection
- Patent number 12,079,082
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Christophe Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unbalanced programmed data states in memory
- Patent number 12,068,016
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Christophe Laurent
- G11 - INFORMATION STORAGE
Information Patent Grant
Bank configurable power modes
- Patent number 12,045,113
- Issue date Jul 23, 2024
- Micron Technology, Inc.
- Graziano Mirichigni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing multiple error correction code protection levels in memory
- Patent number 12,039,176
- Issue date Jul 16, 2024
- Micron Technology, Inc.
- Marco Sforzin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared decoder architecture for three-dimensional memory arrays
- Patent number 11,967,372
- Issue date Apr 23, 2024
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel access in a memory array
- Patent number 11,915,740
- Issue date Feb 27, 2024
- Micron Technology, Inc.
- Efrem Bolandrina
- G11 - INFORMATION STORAGE
Information Patent Grant
Generating a protected and balanced codeword
- Patent number 11,914,476
- Issue date Feb 27, 2024
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fixed weight codewords for ternary memory cells
- Patent number 11,811,424
- Issue date Nov 7, 2023
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture-based power management for a memory device
- Patent number 11,740,678
- Issue date Aug 29, 2023
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared error correction coding circuitry
- Patent number 11,742,047
- Issue date Aug 29, 2023
- Micron Technology, Inc.
- Marco Sforzin
- G11 - INFORMATION STORAGE
Information Patent Grant
Balancing data for storage in a memory device
- Patent number 11,733,913
- Issue date Aug 22, 2023
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating a balanced codeword protected by an error correction code
- Patent number 11,687,411
- Issue date Jun 27, 2023
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating a protected and balanced codeword
- Patent number 11,567,831
- Issue date Jan 31, 2023
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating a protected and balanced codeword
- Patent number 11,494,264
- Issue date Nov 8, 2022
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Active boundary quilt architecture memory
- Patent number 11,355,162
- Issue date Jun 7, 2022
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Balancing data for storage in a memory device
- Patent number 11,262,937
- Issue date Mar 1, 2022
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture-based power management for a memory device
- Patent number 11,243,596
- Issue date Feb 8, 2022
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating a balanced codeword protected by an error correction code
- Patent number 11,237,906
- Issue date Feb 1, 2022
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power domain switches for switching power reduction
- Patent number 11,205,469
- Issue date Dec 21, 2021
- Micron Technology, Inc.
- Stefan Frederik Schippers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient utilization of memory die area
- Patent number 11,170,850
- Issue date Nov 9, 2021
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND SYSTEMS FOR IMPROVING ECC OPERATION OF MEMORIES
- Publication number 20250226046
- Publication date Jul 10, 2025
- Micron Technology, Inc.
- Christophe Laurent
- G11 - INFORMATION STORAGE
Information Patent Application
ECC CONFIGURATION IN MEMORIES
- Publication number 20250061023
- Publication date Feb 20, 2025
- Micron Technology, Inc.
- Graziano Mirichigni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR MANAGING MEMORY WITH DYNAMIC ECC PROTECTION
- Publication number 20240419548
- Publication date Dec 19, 2024
- Micron Technology, Inc.
- Christophe Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ECC POWER CONSUMPTION OPTIMIZATION IN MEMORIES
- Publication number 20240411642
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNBALANCED PROGRAMMED DATA STATES IN MEMORY
- Publication number 20240412768
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Christophe Laurent
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH DATA SCRUBBING CAPABILITY AND METHODS
- Publication number 20240393961
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Graziano Mirichigni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING MULTIPLE ERROR CORRECTION CODE PROTECTION LEVELS IN MEMORY
- Publication number 20240370186
- Publication date Nov 7, 2024
- Micron Technology, Inc.
- Marco Sforzin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CODE CORRECTION COHERENCY CHECKS FOR TERNARY CELL-BASED MEMOR...
- Publication number 20240354189
- Publication date Oct 24, 2024
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST MULTI-PAYLOAD-LENGTH ERROR-CORRECTING SYSTEM AND METHODS
- Publication number 20240356567
- Publication date Oct 24, 2024
- Micron Technology, Inc.
- Marco Sforzin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST MULTI-PAYLOAD-LENGTH ERROR-CORRECTING SYSTEM AND METHODS
- Publication number 20240356566
- Publication date Oct 24, 2024
- Micron Technology, Inc.
- Marco Sforzin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
BANK CONFIGURABLE POWER MODES
- Publication number 20240353914
- Publication date Oct 24, 2024
- Micron Technology, Inc.
- Graziano Mirichigni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED DECODER ARCHITECTURE FOR THREE-DIMENSIONAL MEMORY ARRAYS
- Publication number 20240321349
- Publication date Sep 26, 2024
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G11 - INFORMATION STORAGE
Information Patent Application
PERFECTLY BALANCED ERROR CODE CORRECTION WITHOUT CORRECTION POWER I...
- Publication number 20240291505
- Publication date Aug 29, 2024
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
BALANCED ERROR CORRECTION CODE INCLUDING EXPLICIT QUANTIZED KNUTH I...
- Publication number 20240289216
- Publication date Aug 29, 2024
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL ACCESS IN A MEMORY ARRAY
- Publication number 20240274183
- Publication date Aug 15, 2024
- Micron Technology, Inc.
- Efrem Bolandrina
- G11 - INFORMATION STORAGE
Information Patent Application
GENERATING A PROTECTED AND BALANCED CODEWORD
- Publication number 20240272985
- Publication date Aug 15, 2024
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED ERROR CODE CORRECTION POWER FOR MLC CODEWORDS
- Publication number 20240241789
- Publication date Jul 18, 2024
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE HAVING CACHE STORING CACHE DATA AND SCRUB DATA
- Publication number 20240232095
- Publication date Jul 11, 2024
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR REDUCING ECC POWER CONSUMPTION
- Publication number 20240221857
- Publication date Jul 4, 2024
- Micron Technology, Inc.
- Christophe Laurent
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE HAVING AN IMPROVED ECC ARCHITECTURE
- Publication number 20240221856
- Publication date Jul 4, 2024
- Micron Technology, Inc.
- Christophe Laurent
- G11 - INFORMATION STORAGE
Information Patent Application
IMPROVED ECC CONFIGURATION IN MEMORIES
- Publication number 20240211347
- Publication date Jun 27, 2024
- Micron Technology, Inc.
- Graziano Mirichigni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR MANAGING MEMORY WITH DYNAMIC ECC PROTECTION
- Publication number 20240211346
- Publication date Jun 27, 2024
- Micron Technology, Inc.
- Christophe Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR IMPROVING ECC OPERATION OF MEMORIES
- Publication number 20240194284
- Publication date Jun 13, 2024
- Micron Technology, Inc.
- Christophe Laurent
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE HAVING CACHE STORING CACHE DATA AND SCRUB DATA
- Publication number 20240134802
- Publication date Apr 25, 2024
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING MULTIPLE ERROR CORRECTION CODE PROTECTION LEVELS IN MEMORY
- Publication number 20240103741
- Publication date Mar 28, 2024
- Micron Technology, Inc.
- Marco Sforzin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING MODE FOR ACCESSING MEMORY CELLS IN A MEMORY DEVICE
- Publication number 20240071476
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Andrea Martinelli
- G11 - INFORMATION STORAGE
Information Patent Application
DRIFT CORRECTION IN SLC AND MLC MEMORY DEVICES
- Publication number 20240071483
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BALANCED CODEWORDS FOR REDUCING A SELECTED STATE IN MEMORY CELLS
- Publication number 20240053902
- Publication date Feb 15, 2024
- Micron Technology, Inc.
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING SENSE OPERATIONS IN MEMORY
- Publication number 20240038322
- Publication date Feb 1, 2024
- Micron Technology, Inc.
- Michele Maria Venturini
- G11 - INFORMATION STORAGE
Information Patent Application
ARCHITECTURE-BASED POWER MANAGEMENT FOR A MEMORY DEVICE
- Publication number 20240028099
- Publication date Jan 25, 2024
- Lodestar Licensing Group, LLC
- Christophe Vincent Antoine Laurent
- G06 - COMPUTING CALCULATING COUNTING

Christophe Laurent

Person

Patents Grantslast 30 patents

Balanced codewords for reducing a selected state in memory cells

Parallel access in a memory array

Memory device having an improved ECC architecture

Performing sense operations in memory

Methods and systems for improving ECC operation of memories

Shared decoder architecture for three-dimensional memory arrays

Architecture-based power management for a memory device

Circuit partitioning for a memory device

ECC configuration in memories

Memory device with data scrubbing capability and methods

Methods and systems for managing memory with dynamic ECC protection

Unbalanced programmed data states in memory

Bank configurable power modes

Providing multiple error correction code protection levels in memory

Shared decoder architecture for three-dimensional memory arrays

Parallel access in a memory array

Generating a protected and balanced codeword

Fixed weight codewords for ternary memory cells

Architecture-based power management for a memory device

Shared error correction coding circuitry

Balancing data for storage in a memory device

Generating a balanced codeword protected by an error correction code

Generating a protected and balanced codeword

Generating a protected and balanced codeword

Active boundary quilt architecture memory

Balancing data for storage in a memory device

Architecture-based power management for a memory device

Generating a balanced codeword protected by an error correction code

Power domain switches for switching power reduction

Efficient utilization of memory die area

Patents Applicationslast 30 patents

METHODS AND SYSTEMS FOR IMPROVING ECC OPERATION OF MEMORIES

ECC CONFIGURATION IN MEMORIES

METHODS AND SYSTEMS FOR MANAGING MEMORY WITH DYNAMIC ECC PROTECTION

ECC POWER CONSUMPTION OPTIMIZATION IN MEMORIES

UNBALANCED PROGRAMMED DATA STATES IN MEMORY

MEMORY DEVICE WITH DATA SCRUBBING CAPABILITY AND METHODS

PROVIDING MULTIPLE ERROR CORRECTION CODE PROTECTION LEVELS IN MEMORY

ERROR CODE CORRECTION COHERENCY CHECKS FOR TERNARY CELL-BASED MEMOR...

FAST MULTI-PAYLOAD-LENGTH ERROR-CORRECTING SYSTEM AND METHODS

FAST MULTI-PAYLOAD-LENGTH ERROR-CORRECTING SYSTEM AND METHODS

BANK CONFIGURABLE POWER MODES

SHARED DECODER ARCHITECTURE FOR THREE-DIMENSIONAL MEMORY ARRAYS

PERFECTLY BALANCED ERROR CODE CORRECTION WITHOUT CORRECTION POWER I...

BALANCED ERROR CORRECTION CODE INCLUDING EXPLICIT QUANTIZED KNUTH I...

PARALLEL ACCESS IN A MEMORY ARRAY

GENERATING A PROTECTED AND BALANCED CODEWORD

REDUCED ERROR CODE CORRECTION POWER FOR MLC CODEWORDS

MEMORY DEVICE HAVING CACHE STORING CACHE DATA AND SCRUB DATA

METHODS AND SYSTEMS FOR REDUCING ECC POWER CONSUMPTION

MEMORY DEVICE HAVING AN IMPROVED ECC ARCHITECTURE

IMPROVED ECC CONFIGURATION IN MEMORIES

METHODS AND SYSTEMS FOR MANAGING MEMORY WITH DYNAMIC ECC PROTECTION

METHODS AND SYSTEMS FOR IMPROVING ECC OPERATION OF MEMORIES

MEMORY DEVICE HAVING CACHE STORING CACHE DATA AND SCRUB DATA

PROVIDING MULTIPLE ERROR CORRECTION CODE PROTECTION LEVELS IN MEMORY

STREAMING MODE FOR ACCESSING MEMORY CELLS IN A MEMORY DEVICE

DRIFT CORRECTION IN SLC AND MLC MEMORY DEVICES

BALANCED CODEWORDS FOR REDUCING A SELECTED STATE IN MEMORY CELLS

PERFORMING SENSE OPERATIONS IN MEMORY

ARCHITECTURE-BASED POWER MANAGEMENT FOR A MEMORY DEVICE