CHRISTOPHER BRYANT

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Processors, methods, systems, and instructions to atomically store...
- Patent number 12,007,938
- Issue date Jun 11, 2024
- Intel Corporation
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined out of order page miss handler
- Patent number 11,822,486
- Issue date Nov 21, 2023
- Intel Corporation
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processors, methods, systems, and instructions to atomically store...
- Patent number 11,347,680
- Issue date May 31, 2022
- Intel Corporation
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processors, methods, systems, and instructions to atomically store...
- Patent number 10,901,940
- Issue date Jan 26, 2021
- Intel Corporation
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for sub-page write protection
- Patent number 10,255,196
- Issue date Apr 9, 2019
- Intel Corporation
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses, methods, and systems for memory disambiguation
- Patent number 10,067,762
- Issue date Sep 4, 2018
- Intel Corporation
- Vikash Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core shared page miss handler
- Patent number 9,921,968
- Issue date Mar 20, 2018
- Intel Corporation
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core shared page miss handler
- Patent number 9,921,967
- Issue date Mar 20, 2018
- Intel Corporation
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core shared page miss handler
- Patent number 9,892,059
- Issue date Feb 13, 2018
- Intel Corporation
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core shared page miss handler
- Patent number 9,892,056
- Issue date Feb 13, 2018
- Intel Corporation
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interruption of a page miss handler
- Patent number 9,875,187
- Issue date Jan 23, 2018
- Intel Corporation
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation lookaside buffer for guest physical addresses in a virt...
- Patent number 9,684,605
- Issue date Jun 20, 2017
- Intel Corporation
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduling scheme for load/store operations
- Patent number 8,769,539
- Issue date Jul 1, 2014
- Advanced Micro Devices, Inc.
- Daniel Hopper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Out-of-order load/store queue structure
- Patent number 8,713,263
- Issue date Apr 29, 2014
- Advanced Micro Devices, Inc.
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined serial ring bus
- Patent number 8,645,588
- Issue date Feb 4, 2014
- Advanced Micro Devices, Inc.
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for controlling a translation lookaside buffer
- Patent number 8,341,316
- Issue date Dec 25, 2012
- Advanced Micro Devices, Inc.
- David Kaplan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for synchronizing data transfer from one domain t...
- Patent number 6,799,280
- Issue date Sep 28, 2004
- Advanced Micro Devices, Inc.
- Robin W. Edenfield
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low-latency circuit for synchronizing data transfers between clock...
- Patent number 6,535,946
- Issue date Mar 18, 2003
- National Semiconductor Corporation
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interbus buffer for use between a pseudo little endian bus and a tr...
- Patent number 5,627,975
- Issue date May 6, 1997
- Motorola, Inc.
- Christopher Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arbitration protocol system granting use of a shared resource to on...
- Patent number 5,392,434
- Issue date Feb 21, 1995
- Motorola, Inc.
- Christopher Bryant
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE...
- Publication number 20240427728
- Publication date Dec 26, 2024
- Intel Corporation
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINED OUT OF ORDER PAGE MISS HANDLER
- Publication number 20240054077
- Publication date Feb 15, 2024
- Intel Corporation
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCHER WITH LOW-LEVEL SOFTWARE CONFIGURABILITY
- Publication number 20230195634
- Publication date Jun 22, 2023
- Intel Corporation
- Krishna Ganapathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE...
- Publication number 20220405234
- Publication date Dec 22, 2022
- Intel Corporation
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINED OUT OF ORDER PAGE MISS HANDLER
- Publication number 20210406194
- Publication date Dec 30, 2021
- Intel Corporation
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE...
- Publication number 20210117372
- Publication date Apr 22, 2021
- Intel Corporation
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, METHODS, AND SYSTEMS FOR MEMORY DISAMBIGUATION
- Publication number 20180004522
- Publication date Jan 4, 2018
- Intel Corporation
- VIKASH AGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE...
- Publication number 20170286113
- Publication date Oct 5, 2017
- Intel Corporation
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SUB-PAGE WRITE PROTECTION
- Publication number 20170177500
- Publication date Jun 22, 2017
- Intel Corporation
- VEDVYAS SHANBHOGUE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CORE SHARED PAGE MISS HANDLER
- Publication number 20170147506
- Publication date May 25, 2017
- Intel Corporation
- CHRISTOPHER D. BRYANT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CORE SHARED PAGE MISS HANDLER
- Publication number 20170116134
- Publication date Apr 27, 2017
- Intel Corporation
- CHRISTOPHER D. BRYANT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CORE SHARED PAGE MISS HANDLER
- Publication number 20170109293
- Publication date Apr 20, 2017
- Intel Corporation
- CHRISTOPHER D. BRYANT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSLATION LOOKASIDE BUFFER FOR GUEST PHYSICAL ADDRESSES IN A VIRT...
- Publication number 20160246732
- Publication date Aug 25, 2016
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERRUPTION OF A PAGE MISS HANDLER
- Publication number 20160170888
- Publication date Jun 16, 2016
- INTEL CORPORATION
- CHRISTOPHER D. BRYANT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CORE SHARED PAGE MISS HANDLER
- Publication number 20130031332
- Publication date Jan 31, 2013
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR REACQUIRING LINES IN A CACHE
- Publication number 20120124296
- Publication date May 17, 2012
- CHRISTOPHER D. BRYANT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCHEDULING SCHEME FOR LOAD/STORE OPERATIONS
- Publication number 20120124586
- Publication date May 17, 2012
- Daniel Hopper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CONTROLLING A TRANSLATION LOOKASIDE BUFFER
- Publication number 20120124325
- Publication date May 17, 2012
- David Kaplan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOAD ORDERING QUEUE
- Publication number 20120117335
- Publication date May 10, 2012
- Advanced Micro Devices, Inc.
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINED SERIAL RING BUS
- Publication number 20120110304
- Publication date May 3, 2012
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OUT-OF-ORDER LOAD/STORE QUEUE STRUCTURE
- Publication number 20120110280
- Publication date May 3, 2012
- Christopher D. Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR HANDLING CRITICAL BLOCKING OF STORE-TO-LOA...
- Publication number 20120059971
- Publication date Mar 8, 2012
- DAVID KAPLAN
- G06 - COMPUTING CALCULATING COUNTING

CHRISTOPHER BRYANT

Person

Patents Grantslast 30 patents

Processors, methods, systems, and instructions to atomically store...

Pipelined out of order page miss handler

Processors, methods, systems, and instructions to atomically store...

Processors, methods, systems, and instructions to atomically store...

Method and apparatus for sub-page write protection

Apparatuses, methods, and systems for memory disambiguation

Multi-core shared page miss handler

Multi-core shared page miss handler

Multi-core shared page miss handler

Multi-core shared page miss handler

Interruption of a page miss handler

Translation lookaside buffer for guest physical addresses in a virt...

Scheduling scheme for load/store operations

Out-of-order load/store queue structure

Pipelined serial ring bus

Method and apparatus for controlling a translation lookaside buffer

System and method for synchronizing data transfer from one domain t...

Low-latency circuit for synchronizing data transfers between clock...

Interbus buffer for use between a pseudo little endian bus and a tr...

Arbitration protocol system granting use of a shared resource to on...

Patents Applicationslast 30 patents

PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE...

PIPELINED OUT OF ORDER PAGE MISS HANDLER

PREFETCHER WITH LOW-LEVEL SOFTWARE CONFIGURABILITY

PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE...

PIPELINED OUT OF ORDER PAGE MISS HANDLER

PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE...

APPARATUSES, METHODS, AND SYSTEMS FOR MEMORY DISAMBIGUATION

PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE...

METHOD AND APPARATUS FOR SUB-PAGE WRITE PROTECTION

MULTI-CORE SHARED PAGE MISS HANDLER

MULTI-CORE SHARED PAGE MISS HANDLER

MULTI-CORE SHARED PAGE MISS HANDLER

TRANSLATION LOOKASIDE BUFFER FOR GUEST PHYSICAL ADDRESSES IN A VIRT...

INTERRUPTION OF A PAGE MISS HANDLER

MULTI-CORE SHARED PAGE MISS HANDLER

METHOD AND APPARATUS FOR REACQUIRING LINES IN A CACHE

SCHEDULING SCHEME FOR LOAD/STORE OPERATIONS

METHOD AND APPARATUS FOR CONTROLLING A TRANSLATION LOOKASIDE BUFFER

LOAD ORDERING QUEUE

PIPELINED SERIAL RING BUS

OUT-OF-ORDER LOAD/STORE QUEUE STRUCTURE

METHOD AND APPARATUS FOR HANDLING CRITICAL BLOCKING OF STORE-TO-LOA...