Christopher E Cox

Person

Baton Rouge, LA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Refresh command control for host assist of row hammer mitigation
- Patent number 11,990,172
- Issue date May 21, 2024
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Periodic calibrations during memory device self refresh
- Patent number 11,790,976
- Issue date Oct 17, 2023
- Intel Corporation
- Christopher E. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Refresh command control for host assist of row hammer mitigation
- Patent number 11,688,452
- Issue date Jun 27, 2023
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input/output (I/O) loopback function for I/O signaling testing
- Patent number 11,662,926
- Issue date May 30, 2023
- Intel Corporation
- Dean-Dexter R. Eugenio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Applying chip select for memory device identification and power man...
- Patent number 11,335,395
- Issue date May 17, 2022
- Intel Corporation
- Christopher E. Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Refresh command control for host assist of row hammer mitigation
- Patent number 11,282,561
- Issue date Mar 22, 2022
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Periodic calibrations during memory device self refresh
- Patent number 11,276,453
- Issue date Mar 15, 2022
- Intel Corporation
- Christopher E. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Representing a cache line bit pattern via meta signaling
- Patent number 11,093,391
- Issue date Aug 17, 2021
- Intel Corporation
- Saher Abu Rahme
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DDR memory bus with a reduced data strobe signal preamble timespan
- Patent number 11,074,959
- Issue date Jul 27, 2021
- Intel Corporation
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficiently training memory device chip select control
- Patent number 11,061,590
- Issue date Jul 13, 2021
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically programmable memory test traffic router
- Patent number 11,042,315
- Issue date Jun 22, 2021
- Intel Corporation
- Lakshminarayana Pappu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input/output (I/O) loopback function for I/O signaling testing
- Patent number 10,969,979
- Issue date Apr 6, 2021
- Intel Corporation
- Dean-Dexter R. Eugenio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Refresh command control for host assist of row hammer mitigation
- Patent number 10,950,288
- Issue date Mar 16, 2021
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snap-on electromagnetic interference (EMI)-shielding without mother...
- Patent number 10,938,161
- Issue date Mar 2, 2021
- Intel Corporation
- Jaejin Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Crosstalk reducing connector pin geometry
- Patent number 10,923,859
- Issue date Feb 16, 2021
- Intel Corporation
- Jaejin Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory module thermal management
- Patent number 10,890,931
- Issue date Jan 12, 2021
- Intel Corporation
- Ishmael Santos
- G05 - CONTROLLING REGULATING
Information Patent Grant
Applying chip select for memory device identification and power man...
- Patent number 10,839,887
- Issue date Nov 17, 2020
- Intel Corporation
- Christopher E. Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Invertible optical float switch
- Patent number 10,840,045
- Issue date Nov 17, 2020
- Christopher E. Cox
- G02 - OPTICS
Information Patent Grant
Memory device with flexible internal data write control circuitry
- Patent number 10,755,753
- Issue date Aug 25, 2020
- Intel Corporation
- Uksong Kang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Periodic calibrations during memory device self refresh
- Patent number 10,692,560
- Issue date Jun 23, 2020
- Intel Corporation
- Christopher E. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Platform debug and testing with secured hardware
- Patent number 10,613,955
- Issue date Apr 7, 2020
- Intel Corporation
- Lakshminarayana Pappu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to change a mode of operation for a memory device
- Patent number 10,599,206
- Issue date Mar 24, 2020
- Intel Corporation
- Christopher E. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to access or operate a dual in-line memory module via mu...
- Patent number 10,592,445
- Issue date Mar 17, 2020
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DDR memory bus with a reduced data strobe signal preamble timespan
- Patent number 10,541,018
- Issue date Jan 21, 2020
- Intel Corporation
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input/output (I/O) loopback function for I/O signaling testing
- Patent number 10,496,309
- Issue date Dec 3, 2019
- Intel Corporation
- Dean-Dexter R. Eugenio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated error checking and correction (ECC) in byte mode memory...
- Patent number 10,482,947
- Issue date Nov 19, 2019
- Intel Corporation
- Christopher E. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Representing a cache line bit pattern via meta signaling
- Patent number 10,430,335
- Issue date Oct 1, 2019
- Intel Corporation
- Saher Abu Rahme
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficiently training memory device chip select control
- Patent number 10,416,912
- Issue date Sep 17, 2019
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reading from a mode register having different read and write timing
- Patent number 10,395,722
- Issue date Aug 27, 2019
- Intel Corporation
- Christopher E. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with flexible internal data write control circuitry
- Patent number 10,249,351
- Issue date Apr 2, 2019
- Intel Corporation
- Uksong Kang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION
- Publication number 20230386548
- Publication date Nov 30, 2023
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION
- Publication number 20220189532
- Publication date Jun 16, 2022
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERIODIC CALIBRATIONS DURING MEMORY DEVICE SELF REFRESH
- Publication number 20220157374
- Publication date May 19, 2022
- Intel Corporation
- Christopher E. COX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INPUT/OUTPUT (I/O) LOOPBACK FUNCTION FOR I/O SIGNALING TESTING
- Publication number 20210247919
- Publication date Aug 12, 2021
- Intel Corporation
- Dean-Dexter R. EUGENIO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION
- Publication number 20210151095
- Publication date May 20, 2021
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...
- Publication number 20210020224
- Publication date Jan 21, 2021
- Intel Corporation
- Christopher E. COX
- G11 - INFORMATION STORAGE
Information Patent Application
PERIODIC CALIBRATIONS DURING MEMORY DEVICE SELF REFRESH
- Publication number 20210005245
- Publication date Jan 7, 2021
- Intel Corporation
- Christopher E. COX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DDR MEMORY BUS WITH A REDUCED DATA STROBE SIGNAL PREAMBLE TIMESPAN
- Publication number 20200286543
- Publication date Sep 10, 2020
- Intel Corporation
- James A. McCALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE PACKAGE WITH NOISE SHIELDING
- Publication number 20200219825
- Publication date Jul 9, 2020
- Intel Corporation
- Jaejin LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INPUT/OUTPUT (I/O) LOOPBACK FUNCTION FOR I/O SIGNALING TESTING
- Publication number 20200159429
- Publication date May 21, 2020
- Intel Corporation
- Dean-Dexter R. EUGENIO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENTLY TRAINING MEMORY DEVICE CHIP SELECT CONTROL
- Publication number 20200110551
- Publication date Apr 9, 2020
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPRESENTING A CACHE LINE BIT PATTERN VIA META SIGNALING
- Publication number 20200057718
- Publication date Feb 20, 2020
- Intel Corporation
- Saher Abu Rahme
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...
- Publication number 20190392886
- Publication date Dec 26, 2019
- Intel Corporation
- Christopher E. COX
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH FLEXIBLE INTERNAL DATA WRITE CONTROL CIRCUITRY
- Publication number 20190252009
- Publication date Aug 15, 2019
- Intel Corporation
- Uksong KANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSSTALK REDUCING CONNECTOR PIN GEOMETRY
- Publication number 20190245309
- Publication date Aug 8, 2019
- Jaejin Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION
- Publication number 20190228813
- Publication date Jul 25, 2019
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SNAP-ON ELECTROMAGNETIC INTERFERENCE (EMI)-SHIELDING WITHOUT MOTHER...
- Publication number 20190229473
- Publication date Jul 25, 2019
- Intel Corporation
- Jaejin LEE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES TO ACCESS OR OPERATE A DUAL IN-LINE MEMORY MODULE VIA MU...
- Publication number 20190213148
- Publication date Jul 11, 2019
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY COMMAND THAT SPECIFIES ONE OF MULTIPLE POSSIBLE WRITE DATA V...
- Publication number 20190163393
- Publication date May 30, 2019
- Intel Corporation
- Christopher E. COX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READING FROM A MODE REGISTER HAVING DIFFERENT READ AND WRITE TIMING
- Publication number 20190103154
- Publication date Apr 4, 2019
- Intel Corporation
- Christopher E. COX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DDR MEMORY BUS WITH A REDUCED DATA STROBE SIGNAL PREAMBLE TIMESPAN
- Publication number 20190096468
- Publication date Mar 28, 2019
- James A. McCALL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY PROGRAMMABLE MEMORY TEST TRAFFIC ROUTER
- Publication number 20190042131
- Publication date Feb 7, 2019
- Intel Corporation
- Lakshminarayana PAPPU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLATFORM DEBUG AND TESTING WITH SECURED HARDWARE
- Publication number 20190042382
- Publication date Feb 7, 2019
- Intel Corporation
- Lakshminarayana PAPPU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERIODIC CALIBRATIONS DURING MEMORY DEVICE SELF REFRESH
- Publication number 20190043557
- Publication date Feb 7, 2019
- Intel Corporation
- Christopher E. COX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO CHANGE A MODE OF OPERATION FOR A MEMORY DEVICE
- Publication number 20180348838
- Publication date Dec 6, 2018
- Intel Corporation
- Christopher E. COX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCTION OF POWER CONSUMPTION IN MEMORY DEVICES DURING REFRESH MODES
- Publication number 20180336943
- Publication date Nov 22, 2018
- Intel Corporation
- Christopher E. COX
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED ERROR CHECKING AND CORRECTION (ECC) IN BYTE MODE MEMORY...
- Publication number 20180254079
- Publication date Sep 6, 2018
- Intel Corporation
- Christopher E. COX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INPUT/OUTPUT (I/O) LOOPBACK FUNCTION FOR I/O SIGNALING TESTING
- Publication number 20180136866
- Publication date May 17, 2018
- Intel Corporation
- Dean-Dexter R. EUGENIO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH FLEXIBLE INTERNAL DATA WRITE CONTROL CIRCUITRY
- Publication number 20180130506
- Publication date May 10, 2018
- Intel Corporation
- Uksong KANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENTLY TRAINING MEMORY DEVICE CHIP SELECT CONTROL
- Publication number 20180121123
- Publication date May 3, 2018
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING

Christopher E Cox

Person

Patents Grantslast 30 patents

Refresh command control for host assist of row hammer mitigation

Periodic calibrations during memory device self refresh

Refresh command control for host assist of row hammer mitigation

Input/output (I/O) loopback function for I/O signaling testing

Applying chip select for memory device identification and power man...

Refresh command control for host assist of row hammer mitigation

Periodic calibrations during memory device self refresh

Representing a cache line bit pattern via meta signaling

DDR memory bus with a reduced data strobe signal preamble timespan

Efficiently training memory device chip select control

Dynamically programmable memory test traffic router

Input/output (I/O) loopback function for I/O signaling testing

Refresh command control for host assist of row hammer mitigation

Snap-on electromagnetic interference (EMI)-shielding without mother...

Crosstalk reducing connector pin geometry

Memory module thermal management

Applying chip select for memory device identification and power man...

Invertible optical float switch

Memory device with flexible internal data write control circuitry

Periodic calibrations during memory device self refresh

Platform debug and testing with secured hardware

Techniques to change a mode of operation for a memory device

Techniques to access or operate a dual in-line memory module via mu...

DDR memory bus with a reduced data strobe signal preamble timespan

Input/output (I/O) loopback function for I/O signaling testing

Integrated error checking and correction (ECC) in byte mode memory...

Representing a cache line bit pattern via meta signaling

Efficiently training memory device chip select control

Reading from a mode register having different read and write timing

Memory device with flexible internal data write control circuitry

Patents Applicationslast 30 patents

REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION

REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION

PERIODIC CALIBRATIONS DURING MEMORY DEVICE SELF REFRESH

INPUT/OUTPUT (I/O) LOOPBACK FUNCTION FOR I/O SIGNALING TESTING

REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION

APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...

PERIODIC CALIBRATIONS DURING MEMORY DEVICE SELF REFRESH

DDR MEMORY BUS WITH A REDUCED DATA STROBE SIGNAL PREAMBLE TIMESPAN

MEMORY DEVICE PACKAGE WITH NOISE SHIELDING

INPUT/OUTPUT (I/O) LOOPBACK FUNCTION FOR I/O SIGNALING TESTING

EFFICIENTLY TRAINING MEMORY DEVICE CHIP SELECT CONTROL

REPRESENTING A CACHE LINE BIT PATTERN VIA META SIGNALING

APPLYING CHIP SELECT FOR MEMORY DEVICE IDENTIFICATION AND POWER MAN...

MEMORY DEVICE WITH FLEXIBLE INTERNAL DATA WRITE CONTROL CIRCUITRY

CROSSTALK REDUCING CONNECTOR PIN GEOMETRY

REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION

SNAP-ON ELECTROMAGNETIC INTERFERENCE (EMI)-SHIELDING WITHOUT MOTHER...

TECHNIQUES TO ACCESS OR OPERATE A DUAL IN-LINE MEMORY MODULE VIA MU...

MEMORY COMMAND THAT SPECIFIES ONE OF MULTIPLE POSSIBLE WRITE DATA V...

READING FROM A MODE REGISTER HAVING DIFFERENT READ AND WRITE TIMING

DDR MEMORY BUS WITH A REDUCED DATA STROBE SIGNAL PREAMBLE TIMESPAN

DYNAMICALLY PROGRAMMABLE MEMORY TEST TRAFFIC ROUTER

PLATFORM DEBUG AND TESTING WITH SECURED HARDWARE

PERIODIC CALIBRATIONS DURING MEMORY DEVICE SELF REFRESH

TECHNIQUES TO CHANGE A MODE OF OPERATION FOR A MEMORY DEVICE

REDUCTION OF POWER CONSUMPTION IN MEMORY DEVICES DURING REFRESH MODES

INTEGRATED ERROR CHECKING AND CORRECTION (ECC) IN BYTE MODE MEMORY...

INPUT/OUTPUT (I/O) LOOPBACK FUNCTION FOR I/O SIGNALING TESTING

MEMORY DEVICE WITH FLEXIBLE INTERNAL DATA WRITE CONTROL CIRCUITRY

EFFICIENTLY TRAINING MEMORY DEVICE CHIP SELECT CONTROL