Christopher J. Nelson

Person

Gilbert, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Compressed test patterns for a field programmable gate array
- Patent number 11,193,975
- Issue date Dec 7, 2021
- Intel Corportion
- Christopher J. Nelson
- G01 - MEASURING TESTING
Information Patent Grant
Systems, methods, and apparatuses for implementing die recovery in...
- Patent number 10,249,597
- Issue date Apr 2, 2019
- Intel Corporation
- Lakshminarayana Pappu
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit package with embedded bridge
- Patent number 10,068,852
- Issue date Sep 4, 2018
- Intel Corporation
- Ravindranath V. Mahajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked semiconductor package having fault detection and a method f...
- Patent number 9,972,611
- Issue date May 15, 2018
- Intel Corporation
- Lakshminarayana Pappu
- G11 - INFORMATION STORAGE
Information Patent Grant
High density interconnection of microelectronic devices
- Patent number 9,842,832
- Issue date Dec 12, 2017
- Intel Corporation
- Omkar G. Karhade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with embedded bridge
- Patent number 9,716,067
- Issue date Jul 25, 2017
- Intel Corporation
- Ravindranath V. Mahajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Duty cycle based timing margining for I/O AC timing
- Patent number 9,535,119
- Issue date Jan 3, 2017
- Intel Corporation
- Bharani Thiruvengadam
- G01 - MEASURING TESTING
Information Patent Grant
Testing I/O timing defects for high pin count, non-contact interfaces
- Patent number 9,501,376
- Issue date Nov 22, 2016
- Intel Corporation
- Christopher Nelson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High density interconnection of microelectronic devices
- Patent number 9,397,071
- Issue date Jul 19, 2016
- Intel Corporation
- Omkar G. Karhade
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit package with embedded bridge
- Patent number 9,275,955
- Issue date Mar 1, 2016
- Intel Corporation
- Ravindranath V. Mahajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Input/output delay testing for devices utilizing on-chip delay gene...
- Patent number 9,110,134
- Issue date Aug 18, 2015
- Intel Corporation
- Tak M. Mak
- G01 - MEASURING TESTING
Information Patent Grant
Method, system and apparatus for evaluation of input/output buffer...
- Patent number 8,843,794
- Issue date Sep 23, 2014
- Intel Corporation
- Christopher J. Nelson
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed VLSI digital tester architecture for real-time output ti...
- Patent number 6,768,297
- Issue date Jul 27, 2004
- Intel Corporation
- John C. Johnson
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for testing an integrated circuit having an ou...
- Patent number 6,693,436
- Issue date Feb 17, 2004
- Intel Corporation
- Christopher J. Nelson
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
COMPRESSED TEST PATTERNS FOR A FIELD PROGRAMMABLE GATE ARRAY
- Publication number 20200003836
- Publication date Jan 2, 2020
- Intel Corporation
- Christopher J. NELSON
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING DIE RECOVERY IN...
- Publication number 20180096971
- Publication date Apr 5, 2018
- Intel Corporation
- LAKSHMINARAYANA PAPPU
- G11 - INFORMATION STORAGE
Information Patent Application
A STACKED SEMICONDUCTOR PACKAGE HAVING FAULT DETECTION AND A METHOD...
- Publication number 20180096979
- Publication date Apr 5, 2018
- Intel Corporation
- LAKSHMINARAYANA PAPPU
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH EMBEDDED BRIDGE
- Publication number 20170301625
- Publication date Oct 19, 2017
- Intel Corporation
- Ravindranath V. Mahajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY INTERCONNECTION OF MICROELECTRONIC DEVICES
- Publication number 20160300824
- Publication date Oct 13, 2016
- Intel Corporation
- Omkar G. Karhade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH EMBEDDED BRIDGE
- Publication number 20160155705
- Publication date Jun 2, 2016
- Intel Corporation
- Ravindranath V. Mahajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUTY CYCLE BASED TIMING MARGINING FOR I/O AC TIMING
- Publication number 20150377967
- Publication date Dec 31, 2015
- BHARANI THIRUVENGADAM
- G01 - MEASURING TESTING
Information Patent Application
TESTING I/O TIMING DEFECTS FOR HIGH PIN COUNT, NON-CONTACT INTERFACES
- Publication number 20150324265
- Publication date Nov 12, 2015
- CHRISTOPHER NELSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING A WIDE FUNCTIONAL INTERFACE OF A DEVICE INTEGRATED ON AN SI...
- Publication number 20150187410
- Publication date Jul 2, 2015
- Christopher J Nelson
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH EMBEDDED BRIDGE
- Publication number 20150171015
- Publication date Jun 18, 2015
- Ravindranath V. Mahajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY INTERCONNECTION OF MICROELECTRONIC DEVICES
- Publication number 20150163904
- Publication date Jun 11, 2015
- Intel Corporation
- Omkar G. Karhade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INPUT/OUTPUT DELAY TESTING FOR DEVICES UTILIZING ON-CHIP DELAY GENE...
- Publication number 20140189457
- Publication date Jul 3, 2014
- Tak M. Mak
- G01 - MEASURING TESTING
Information Patent Application
METHOD, SYSTEM AND APPARATUS FOR EVALUATION OF INPUT/OUTPUT BUFFER...
- Publication number 20140089752
- Publication date Mar 27, 2014
- Christopher J. Nelson
- G01 - MEASURING TESTING
Information Patent Application
High speed VLSI digital tester architecture for real-time output ti...
- Publication number 20020063556
- Publication date May 30, 2002
- Intel Corporation
- John C. Johnson
- G01 - MEASURING TESTING

Christopher J. Nelson

Person

Patents Grantslast 30 patents

Compressed test patterns for a field programmable gate array

Systems, methods, and apparatuses for implementing die recovery in...

Integrated circuit package with embedded bridge

Stacked semiconductor package having fault detection and a method f...

High density interconnection of microelectronic devices

Integrated circuit package with embedded bridge

Duty cycle based timing margining for I/O AC timing

Testing I/O timing defects for high pin count, non-contact interfaces

High density interconnection of microelectronic devices

Integrated circuit package with embedded bridge

Input/output delay testing for devices utilizing on-chip delay gene...

Method, system and apparatus for evaluation of input/output buffer...

High speed VLSI digital tester architecture for real-time output ti...

Method and apparatus for testing an integrated circuit having an ou...

Patents Applicationslast 30 patents

COMPRESSED TEST PATTERNS FOR A FIELD PROGRAMMABLE GATE ARRAY

SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING DIE RECOVERY IN...

A STACKED SEMICONDUCTOR PACKAGE HAVING FAULT DETECTION AND A METHOD...

INTEGRATED CIRCUIT PACKAGE WITH EMBEDDED BRIDGE

HIGH DENSITY INTERCONNECTION OF MICROELECTRONIC DEVICES

INTEGRATED CIRCUIT PACKAGE WITH EMBEDDED BRIDGE

DUTY CYCLE BASED TIMING MARGINING FOR I/O AC TIMING

TESTING I/O TIMING DEFECTS FOR HIGH PIN COUNT, NON-CONTACT INTERFACES

TESTING A WIDE FUNCTIONAL INTERFACE OF A DEVICE INTEGRATED ON AN SI...

INTEGRATED CIRCUIT PACKAGE WITH EMBEDDED BRIDGE

HIGH DENSITY INTERCONNECTION OF MICROELECTRONIC DEVICES

INPUT/OUTPUT DELAY TESTING FOR DEVICES UTILIZING ON-CHIP DELAY GENE...

METHOD, SYSTEM AND APPARATUS FOR EVALUATION OF INPUT/OUTPUT BUFFER...

High speed VLSI digital tester architecture for real-time output ti...