Christopher Prindle

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Gate-all-around transistor with spacer support and methods of formi...
- Patent number 10,734,525
- Issue date Aug 4, 2020
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Removal of epitaxy defects in transistors
- Patent number 10,699,965
- Issue date Jun 30, 2020
- International Business Machines Corporation
- Andrew Greene
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate and source/drain contact structures positioned above an active...
- Patent number 10,388,770
- Issue date Aug 20, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate contact structure positioned above an active region with air g...
- Patent number 10,388,747
- Issue date Aug 20, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming epi semiconductor material on a recessed fin in...
- Patent number 10,290,738
- Issue date May 14, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit products that include FinFET devices and a prote...
- Patent number 10,170,544
- Issue date Jan 1, 2019
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods, apparatus and system for providing source-drain epitaxy la...
- Patent number 10,068,978
- Issue date Sep 4, 2018
- GLOBALFOUNDRIES Inc.
- Kwan-Yong Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of forming a protection layer on an isolation region of IC...
- Patent number 9,876,077
- Issue date Jan 23, 2018
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET spacer formation on gate sidewalls, between the channel and...
- Patent number 9,806,078
- Issue date Oct 31, 2017
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Devices and methods of forming epi for aggressive gate pitch
- Patent number 9,685,384
- Issue date Jun 20, 2017
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods, apparatus and system for providing source-drain epitaxy la...
- Patent number 9,640,533
- Issue date May 2, 2017
- GLOBALFOUNDRIES Inc.
- Kwan-Yong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices with dummy gate structures partially on isola...
- Patent number 9,496,354
- Issue date Nov 15, 2016
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Raised source/drain EPI with suppressed lateral EPI overgrowth
- Patent number 9,236,452
- Issue date Jan 12, 2016
- GLOBALFOUNDRIES INC.
- Kwan-Yong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor(s) with different source/drain channel junction characte...
- Patent number 9,230,802
- Issue date Jan 5, 2016
- GLOBALFOUNDRIES Inc.
- Neeraj Tripathi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming gate structures for semiconductor devices using...
- Patent number 9,184,263
- Issue date Nov 10, 2015
- GLOBALFOUNDRIES Inc.
- Xiuyu Cai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming replacement spacer structures on semiconductor d...
- Patent number 9,147,748
- Issue date Sep 29, 2015
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two step optical planarizing layer etch
- Patent number 7,601,641
- Issue date Oct 13, 2009
- Global Foundries, Inc.
- Erik Geiss
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
GATE-ALL-AROUND TRANSISTOR WITH SPACER SUPPORT AND METHODS OF FORMI...
- Publication number 20190288117
- Publication date Sep 19, 2019
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT TO SOURCE/DRAIN REGIONS AND METHOD OF FORMING SAME
- Publication number 20190081145
- Publication date Mar 14, 2019
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL ON A RECESSED FIN IN...
- Publication number 20180294348
- Publication date Oct 11, 2018
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PRODUCTS THAT INCLUDE FINFET DEVICES AND A PROTE...
- Publication number 20180102409
- Publication date Apr 12, 2018
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING A PROTECTION LAYER ON AN ISOLATION REGION OF IC...
- Publication number 20180006111
- Publication date Jan 4, 2018
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS, APPARATUS AND SYSTEM FOR PROVIDING SOURCE-DRAIN EPITAXY LA...
- Publication number 20170200797
- Publication date Jul 13, 2017
- GLOBALFOUNDRIES INC.
- Kwan-Yong Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS, APPARATUS AND SYSTEM FOR PROVIDING SOURCE-DRAIN EPITAXY LA...
- Publication number 20160268257
- Publication date Sep 15, 2016
- GLOBALFOUNDRIES INC.
- Kwan-Yong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RAISED SOURCE/DRAIN EPI WITH SUPPRESSED LATERAL EPI OVERGROWTH
- Publication number 20160056238
- Publication date Feb 25, 2016
- GLOBALFOUNDRIES INC.
- Kwan-Yong LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RAISED SOURCE/DRAIN EPI WITH SUPPRESSED LATERAL EPI OVERGROWTH
- Publication number 20150340471
- Publication date Nov 26, 2015
- GLOBALFOUNDRIES INC.
- Kwan-Yong LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED CHANNEL FIN DEVICE WITH RAISED SOURCE AND DRAIN REGIONS
- Publication number 20150340468
- Publication date Nov 26, 2015
- GLOBALFOUNDRIES INC.
- Kwan-Yong Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR(S) WITH DIFFERENT SOURCE/DRAIN CHANNEL JUNCTION CHARACTE...
- Publication number 20150340229
- Publication date Nov 26, 2015
- GLOBALFOUNDRIES INC.
- Neeraj TRIPATHI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICES WITH REPLACEMENT SPACER STRUCTURES
- Publication number 20150333136
- Publication date Nov 19, 2015
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING GATE STRUCTURES FOR SEMICONDUCTOR DEVICES USING...
- Publication number 20150187905
- Publication date Jul 2, 2015
- GLOBALFOUNDRIES INC.
- Xiuyu Cai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH IMPROVED CONTACT PLUGS, AND RELATED FABRI...
- Publication number 20100072623
- Publication date Mar 25, 2010
- Advanced Micro Devices, Inc.
- Christopher M. PRINDLE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO STEP OPTICAL PLANARIZING LAYER ETCH
- Publication number 20090246959
- Publication date Oct 1, 2009
- Advanced Micro Devices, Inc.
- Erik GEISS
- H01 - BASIC ELECTRIC ELEMENTS

Christopher Prindle

Person

Patents Grantslast 30 patents

Gate-all-around transistor with spacer support and methods of formi...

Removal of epitaxy defects in transistors

Gate and source/drain contact structures positioned above an active...

Gate contact structure positioned above an active region with air g...

Methods of forming epi semiconductor material on a recessed fin in...

Integrated circuit products that include FinFET devices and a prote...

Methods, apparatus and system for providing source-drain epitaxy la...

Methods of forming a protection layer on an isolation region of IC...

FinFET spacer formation on gate sidewalls, between the channel and...

Devices and methods of forming epi for aggressive gate pitch

Methods, apparatus and system for providing source-drain epitaxy la...

Semiconductor devices with dummy gate structures partially on isola...

Raised source/drain EPI with suppressed lateral EPI overgrowth

Transistor(s) with different source/drain channel junction characte...

Methods of forming gate structures for semiconductor devices using...

Methods of forming replacement spacer structures on semiconductor d...

Two step optical planarizing layer etch

Patents Applicationslast 30 patents

GATE-ALL-AROUND TRANSISTOR WITH SPACER SUPPORT AND METHODS OF FORMI...

CONTACT TO SOURCE/DRAIN REGIONS AND METHOD OF FORMING SAME

METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL ON A RECESSED FIN IN...

INTEGRATED CIRCUIT PRODUCTS THAT INCLUDE FINFET DEVICES AND A PROTE...

METHODS OF FORMING A PROTECTION LAYER ON AN ISOLATION REGION OF IC...

METHODS, APPARATUS AND SYSTEM FOR PROVIDING SOURCE-DRAIN EPITAXY LA...

METHODS, APPARATUS AND SYSTEM FOR PROVIDING SOURCE-DRAIN EPITAXY LA...

RAISED SOURCE/DRAIN EPI WITH SUPPRESSED LATERAL EPI OVERGROWTH

RAISED SOURCE/DRAIN EPI WITH SUPPRESSED LATERAL EPI OVERGROWTH

RECESSED CHANNEL FIN DEVICE WITH RAISED SOURCE AND DRAIN REGIONS

TRANSISTOR(S) WITH DIFFERENT SOURCE/DRAIN CHANNEL JUNCTION CHARACTE...

SEMICONDUCTOR DEVICES WITH REPLACEMENT SPACER STRUCTURES

METHODS OF FORMING GATE STRUCTURES FOR SEMICONDUCTOR DEVICES USING...

SEMICONDUCTOR DEVICE WITH IMPROVED CONTACT PLUGS, AND RELATED FABRI...

TWO STEP OPTICAL PLANARIZING LAYER ETCH