Christopher S. Norris

Person

Morgan Hill, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory architecture for burst mode access
- Patent number 5,831,926
- Issue date Nov 3, 1998
- Cypress Semiconductor Corp.
- Christopher S. Norris
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture for burst mode access
- Patent number 5,787,047
- Issue date Jul 28, 1998
- Cypress Semiconductor Corp.
- Christopher S. Norris
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed flash memory cell structure and method
- Patent number 5,760,438
- Issue date Jun 2, 1998
- Cypress Semiconductor Corporation
- Rakesh Balraj Sethi
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage reference and measurement circuit for verifying a prog...
- Patent number 5,710,778
- Issue date Jan 20, 1998
- Cyrpress Semiconductor Corporation
- Roger J. Bettman
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed flash memory cell structure and method
- Patent number 5,648,669
- Issue date Jul 15, 1997
- Cypress Semiconductor
- Rakesh Balraj Sethi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture for burst mode access
- Patent number 5,453,957
- Issue date Sep 26, 1995
- Cypress Semiconductor Corp.
- Christopher S. Norris
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with minimized redundancy access delay
- Patent number 5,381,370
- Issue date Jan 10, 1995
- Cypress Semiconductor Corporation
- Timothy M. Lacey
- G11 - INFORMATION STORAGE
Information Patent Grant
EPROM source bias circuit with compensation for processing characte...
- Patent number 5,218,571
- Issue date Jun 8, 1993
- Cypress Semiconductor Corporation
- Chris Norris
- G11 - INFORMATION STORAGE

Christopher S. Norris

Person

Patents Grantslast 30 patents

Memory architecture for burst mode access

Memory architecture for burst mode access

High speed flash memory cell structure and method

High voltage reference and measurement circuit for verifying a prog...

High speed flash memory cell structure and method

Memory architecture for burst mode access

Memory with minimized redundancy access delay

EPROM source bias circuit with compensation for processing characte...