Chuan-Cheng Cheng

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Isolation components for transistors formed on fin features of semi...
- Patent number 10,784,167
- Issue date Sep 22, 2020
- Marvell Asia Pte, Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation components for transistors formed on fin features of semi...
- Patent number 10,217,669
- Issue date Feb 26, 2019
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package assembly including a semiconductor substrate in which a fir...
- Patent number 9,768,144
- Issue date Sep 19, 2017
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for mitigating effects of parasitic capacitanc...
- Patent number 9,397,218
- Issue date Jul 19, 2016
- Marvell World Trade Ltd.
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recessed semiconductor substrates and associated techniques
- Patent number 9,391,045
- Issue date Jul 12, 2016
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
RC networks that include an integrated high resistance resistor on...
- Patent number 9,275,985
- Issue date Mar 1, 2016
- Marvell International Ltd.
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package assembly having a semiconductor substrate
- Patent number 9,275,929
- Issue date Mar 1, 2016
- Marvell World Trade Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package assembly including a semiconductor substrate in which a fir...
- Patent number 9,257,410
- Issue date Feb 9, 2016
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recessed semiconductor substrates and associated techniques
- Patent number 9,034,730
- Issue date May 19, 2015
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power/ground layout for chips
- Patent number 8,946,890
- Issue date Feb 3, 2015
- Marvell World Trade Ltd.
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Laterally diffused metal oxide semiconductor (LDMOS) device with ov...
- Patent number 8,921,938
- Issue date Dec 30, 2014
- Marvell International Ltd.
- Xin Yi Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High resistivity substrate for integrated passive device (IPD) appl...
- Patent number 8,861,214
- Issue date Oct 14, 2014
- Marvell International Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit devices with electrostatic discharge (ESD) prote...
- Patent number 8,753,960
- Issue date Jun 17, 2014
- Marvell International Ltd.
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit devices with ESD protection in scribe line, and...
- Patent number 8,372,729
- Issue date Feb 12, 2013
- Marvell International Ltd.
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit devices with ESD protection in scribe line, and...
- Patent number 8,049,249
- Issue date Nov 1, 2011
- Marvell International Ltd.
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress tolerant differential colpitts voltage controlled oscillators
- Patent number 8,044,733
- Issue date Oct 25, 2011
- Marvell International Ltd.
- Himanshu Arora
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of fabricating a device with ESD and I/O protection
- Patent number 7,883,947
- Issue date Feb 8, 2011
- Marvell International Ltd.
- Chuan-Cheng Cheng
- G01 - MEASURING TESTING
Information Patent Grant
Methods of making and using fuse structures, and integrated circuit...
- Patent number 7,820,493
- Issue date Oct 26, 2010
- Marvell International Ltd.
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit devices with ESD and I/O protection
- Patent number 7,808,075
- Issue date Oct 5, 2010
- Marvell International Ltd.
- Chuan-Cheng Cheng
- G01 - MEASURING TESTING
Information Patent Grant
Fuse structures, methods of making and using the same, and integrat...
- Patent number 7,704,805
- Issue date Apr 27, 2010
- Marvell International Ltd.
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fuse structures, methods of making and using the same, and integrat...
- Patent number 7,589,363
- Issue date Sep 15, 2009
- Marvell International Ltd.
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fuse structures, methods of making and using the same, and integrat...
- Patent number 7,344,924
- Issue date Mar 18, 2008
- Marvell International Ltd.
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fuse structures, methods of making and using the same, and integrat...
- Patent number 6,940,107
- Issue date Sep 6, 2005
- Marvell International Ltd.
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low resistance metal interconnect lines and a process for fabricati...
- Patent number 6,815,342
- Issue date Nov 9, 2004
- LSI Logic Corporation
- Chuan-cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated capacitor and fuse
- Patent number 6,627,968
- Issue date Sep 30, 2003
- LSI Logic Corporation
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for simultaneous formation of integrated capacitor and fuse
- Patent number 6,495,426
- Issue date Dec 17, 2002
- LSI Logic Corporation
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Isolation Components for Transistors Formed on Fin Features of Semi...
- Publication number 20190148236
- Publication date May 16, 2019
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMI...
- Publication number 20160329249
- Publication date Nov 10, 2016
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE IN WHICH A FIR...
- Publication number 20160155732
- Publication date Jun 2, 2016
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES
- Publication number 20150279806
- Publication date Oct 1, 2015
- Marvell World Trade Ltd.
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE
- Publication number 20150221577
- Publication date Aug 6, 2015
- Marvell World Trade Ltd.
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR MITIGATING EFFECTS OF PARASITIC CAPACITANC...
- Publication number 20150194518
- Publication date Jul 9, 2015
- Marvell World Trade Ltd.
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER/GROUND LAYOUT FOR CHIPS
- Publication number 20150155202
- Publication date Jun 4, 2015
- Marvell World Trade Ltd.
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES
- Publication number 20140124961
- Publication date May 8, 2014
- Marvell World Trade Ltd.
- Albert WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMI...
- Publication number 20140103452
- Publication date Apr 17, 2014
- Marvell World Trade Ltd.
- Runzi Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER/GROUND LAYOUT FOR CHIPS
- Publication number 20120098127
- Publication date Apr 26, 2012
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES
- Publication number 20110186960
- Publication date Aug 4, 2011
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES
- Publication number 20110186992
- Publication date Aug 4, 2011
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED SEMICONDUCTOR SUBSTRATES
- Publication number 20110186998
- Publication date Aug 4, 2011
- Albert Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE
- Publication number 20110175218
- Publication date Jul 21, 2011
- Shiann-Ming Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated capacitor and fuse
- Publication number 20030060009
- Publication date Mar 27, 2003
- LSI Logic Corporation
- Chuan-Cheng Cheng
- H01 - BASIC ELECTRIC ELEMENTS

Chuan-Cheng Cheng

Person

Patents Grantslast 30 patents

Isolation components for transistors formed on fin features of semi...

Isolation components for transistors formed on fin features of semi...

Package assembly including a semiconductor substrate in which a fir...

Method and apparatus for mitigating effects of parasitic capacitanc...

Recessed semiconductor substrates and associated techniques

RC networks that include an integrated high resistance resistor on...

Package assembly having a semiconductor substrate

Package assembly including a semiconductor substrate in which a fir...

Recessed semiconductor substrates and associated techniques

Power/ground layout for chips

Laterally diffused metal oxide semiconductor (LDMOS) device with ov...

High resistivity substrate for integrated passive device (IPD) appl...

Integrated circuit devices with electrostatic discharge (ESD) prote...

Integrated circuit devices with ESD protection in scribe line, and...

Integrated circuit devices with ESD protection in scribe line, and...

Stress tolerant differential colpitts voltage controlled oscillators

Method of fabricating a device with ESD and I/O protection

Methods of making and using fuse structures, and integrated circuit...

Integrated circuit devices with ESD and I/O protection

Fuse structures, methods of making and using the same, and integrat...

Fuse structures, methods of making and using the same, and integrat...

Fuse structures, methods of making and using the same, and integrat...

Fuse structures, methods of making and using the same, and integrat...

Low resistance metal interconnect lines and a process for fabricati...

Integrated capacitor and fuse

Method for simultaneous formation of integrated capacitor and fuse

Patents Applicationslast 30 patents

Isolation Components for Transistors Formed on Fin Features of Semi...

ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMI...

PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE IN WHICH A FIR...

RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES

PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE

METHOD AND APPARATUS FOR MITIGATING EFFECTS OF PARASITIC CAPACITANC...

POWER/GROUND LAYOUT FOR CHIPS

TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES

ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMI...

POWER/GROUND LAYOUT FOR CHIPS

TECHNIQUES AND CONFIGURATIONS FOR RECESSED SEMICONDUCTOR SUBSTRATES

RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES

RECESSED SEMICONDUCTOR SUBSTRATES

PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE

Integrated capacitor and fuse