Chuan Hu

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit packaging method and integrated packaging circuit
- Patent number 11,335,664
- Issue date May 17, 2022
- SHENZHEN XlUYUAN ELECTRONIC TECHNOLOGY CO., LTD
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging structure and method
- Patent number 11,183,458
- Issue date Nov 23, 2021
- Shenzhen Xiuyuan Electronic Technology Co., Ltd
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit system and packaging method therefor
- Patent number 10,930,634
- Issue date Feb 23, 2021
- Shenzhen Xiuyuan Electronic Technology Co., Ltd
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single layer low cost wafer level packaging for SFF SiP
- Patent number 10,867,961
- Issue date Dec 15, 2020
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit packaging method and integrated packaged circuit
- Patent number 10,867,959
- Issue date Dec 15, 2020
- Shenzhen Xiuyuan Electronic Technology Co., Ltd
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip wiring method and structure
- Patent number 10,847,496
- Issue date Nov 24, 2020
- SHENZHEN XIUYUAN ELECTRONIC TECHNOLOGY CO., LTD
- Chuan Hu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit multichip stacked packaging structure and method
- Patent number 10,615,151
- Issue date Apr 7, 2020
- SHENZHEN XIUYUAN ELECTRONIC TECHNOLOGY CO., LTD
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer package
- Patent number 10,535,634
- Issue date Jan 14, 2020
- Intel Corporation
- Vijay K. Nair
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder in cavity interconnection structures
- Patent number 10,468,367
- Issue date Nov 5, 2019
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged semiconductor die and CTE-engineering die pair
- Patent number 10,381,288
- Issue date Aug 13, 2019
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip-module semiconductor chip package having dense package w...
- Patent number 10,256,211
- Issue date Apr 9, 2019
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Magnetic nanocomposite materials and passive components formed ther...
- Patent number 10,122,089
- Issue date Nov 6, 2018
- Intel Corporation
- Vijay K. Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packaged semiconductor die and CTE-engineering die pair
- Patent number 10,096,535
- Issue date Oct 9, 2018
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single layer low cost wafer level packaging for SFF SiP
- Patent number 10,014,277
- Issue date Jul 3, 2018
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wavy interconnect for bendable and stretchable devices
- Patent number 9,942,980
- Issue date Apr 10, 2018
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electric circuit on flexible substrate
- Patent number 9,930,793
- Issue date Mar 27, 2018
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder in cavity interconnection technology
- Patent number 9,848,490
- Issue date Dec 19, 2017
- Intel Corporation
- Chuan Hu
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Substrate for integrated circuit devices including multi-layer glas...
- Patent number 9,761,514
- Issue date Sep 12, 2017
- Intel Corporation
- Qing Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dense interconnect with solder cap (DISC) formation with laser abla...
- Patent number 9,741,645
- Issue date Aug 22, 2017
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic package having non-coplanar, encapsulated microelec...
- Patent number 9,685,390
- Issue date Jun 20, 2017
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package assemblies including a glass solder mask...
- Patent number 9,673,131
- Issue date Jun 6, 2017
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with pre-molding chip bonding
- Patent number 9,659,885
- Issue date May 23, 2017
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with dielectric or anisotropic conductive (ACF) buildup layer
- Patent number 9,543,197
- Issue date Jan 10, 2017
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder in cavity interconnection structures
- Patent number 9,530,747
- Issue date Dec 27, 2016
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic package having direct contact heat spreader and met...
- Patent number 9,508,675
- Issue date Nov 29, 2016
- Intel Corporation
- Daoqiang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method apparatus and material for radio frequency passives and ante...
- Patent number 9,461,355
- Issue date Oct 4, 2016
- Intel Corporation
- Vijay K. Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Substrate for integrated circuit devices including multi-layer glas...
- Patent number 9,420,707
- Issue date Aug 16, 2016
- Intel Corporation
- Qing Ma
- B32 - LAYERED PRODUCTS
Information Patent Grant
Single layer low cost wafer level packaging for SFF SiP
- Patent number 9,281,292
- Issue date Mar 8, 2016
- Intel Corporation
- Chuan Hu
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Off-plane conductive line interconnects in microelectronic devices
- Patent number 9,072,187
- Issue date Jun 30, 2015
- Intel Corporation
- Chuan Hu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Solder in cavity interconnection structures
- Patent number 9,006,890
- Issue date Apr 14, 2015
- Intel Corporation
- Chuan Hu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
Integrated Circuit Packaging Method and Integrated Packaging Circuit
- Publication number 20200043886
- Publication date Feb 6, 2020
- SHENZHEN XIUYUAN ELECTRONIC TECHNOLOGY CO., LTD
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit system and packaging method therefor
- Publication number 20200006310
- Publication date Jan 2, 2020
- SHENZHEN XIUYUAN ELECTRONIC TECHNOLOGY CO., LTD
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Multichip Stacked Packaging Structure and Method
- Publication number 20190326261
- Publication date Oct 24, 2019
- SHENZHEN XIUYUAN ELECTRONIC TECHNOLOGY CO., LTD
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Packaging Method and Integrated Packaged Circuit
- Publication number 20190326207
- Publication date Oct 24, 2019
- Shenzhen Xiuyuan Electronic Technology Co., Ltd.
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip Wiring Method and Structure
- Publication number 20190295982
- Publication date Sep 26, 2019
- SHENZHEN XIUYUAN ELECTRONIC TECHNOLOGY CO., LTD
- Chuan HU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuit Packaging Structure and Method
- Publication number 20190287909
- Publication date Sep 19, 2019
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED SEMICONDUCTOR DIE AND CTE-ENGINEERING DIE PAIR
- Publication number 20190035711
- Publication date Jan 31, 2019
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGLE LAYER LOW COST WAFER LEVEL PACKAGING FOR SFF SIP
- Publication number 20180301435
- Publication date Oct 18, 2018
- Intel Corporation
- Chuan HU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLDER IN CAVITY INTERCONNECTION STRUCTURES
- Publication number 20180151529
- Publication date May 31, 2018
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYER PACKAGE
- Publication number 20170207170
- Publication date Jul 20, 2017
- Intel Coporation
- Vijay K. NAIR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH DIELECTRIC OR ANISOTROPIC CONDUCTIVE (ACF) BUILDUP LAYER
- Publication number 20170179099
- Publication date Jun 22, 2017
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAVY INTERCONNECT FOR BENDABLE AND STRETCHABLE DEVICES
- Publication number 20170079135
- Publication date Mar 16, 2017
- Chuan HU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MAGNETIC NANOCOMPOSITE MATERIALS AND PASSIVE COMPONENTS FORMED THER...
- Publication number 20160322707
- Publication date Nov 3, 2016
- Intel Corporation
- Vijay K. Nair
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE FOR INTEGRATED CIRCUIT DEVICES INCLUDING MULTI-LAYER GLAS...
- Publication number 20160322290
- Publication date Nov 3, 2016
- Intel Corporation
- Qing Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP-MODULE SEMICONDUCTOR CHIP PACKAGE HAVING DENSE PACKAGE W...
- Publication number 20160293578
- Publication date Oct 6, 2016
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGLE LAYER LOW COST WAFER LEVEL PACKAGING FOR SFF SIP
- Publication number 20160163676
- Publication date Jun 9, 2016
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLDER IN CAVITY INTERCONNECTION STRUCTURES
- Publication number 20160148892
- Publication date May 26, 2016
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRIC CIRCUIT ON FLEXIBLE SUBSTRATE
- Publication number 20150282341
- Publication date Oct 1, 2015
- Intel Corporation
- Chuan Hu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
ELECTRONIC PACKAGE AND METHOD OF FORMING AN ELECTRONIC PACKAGE
- Publication number 20150279824
- Publication date Oct 1, 2015
- Vijay K. Nair
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLDER IN CAVITY INTERCONNECTION STRUCTURES
- Publication number 20150187727
- Publication date Jul 2, 2015
- Intel Corporation
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH PRE-MOLDING CHIP BONDING
- Publication number 20150008595
- Publication date Jan 8, 2015
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE ASSEMBLIES INCLUDING A GLASS SOLDER MASK...
- Publication number 20140299999
- Publication date Oct 9, 2014
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method Apparatus and Material for Radio Frequency Passives and Ante...
- Publication number 20140293529
- Publication date Oct 2, 2014
- Vijay K. Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOLDER IN CAVITY INTERCONNECTION TECHNOLOGY
- Publication number 20140240943
- Publication date Aug 28, 2014
- Chuan Hu
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
PACKAGE WITH DIELECTRIC OR ANISOTROPIC CONDUCTIVE (ACF) BUILDUP LAYER
- Publication number 20140167217
- Publication date Jun 19, 2014
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH PRE-MOLDING CHIP BONDING
- Publication number 20140061954
- Publication date Mar 6, 2014
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OFF-PLANE CONDUCTIVE LINE INTERCONNECTS IN MICROELECTRONIC DEVICES
- Publication number 20140063761
- Publication date Mar 6, 2014
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC PACKAGE HAVING NON-COPLANAR, ENCAPSULATED MICROELEC...
- Publication number 20140048959
- Publication date Feb 20, 2014
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DENSE INTERCONNECT WITH SOLDER CAP (DISC) FORMATION WITH LASER ABLA...
- Publication number 20140035134
- Publication date Feb 6, 2014
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED SEMICONDUCTOR DIE AND CTE-ENGINEERING DIE PAIR
- Publication number 20140001629
- Publication date Jan 2, 2014
- Chuan Hu
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Integrated circuit packaging method and integrated packaging circuit

Integrated circuit packaging structure and method

Integrated circuit system and packaging method therefor

Single layer low cost wafer level packaging for SFF SiP

Integrated circuit packaging method and integrated packaged circuit

Chip wiring method and structure

Integrated circuit multichip stacked packaging structure and method

Multi-layer package

Solder in cavity interconnection structures

Packaged semiconductor die and CTE-engineering die pair

Multi-chip-module semiconductor chip package having dense package w...

Magnetic nanocomposite materials and passive components formed ther...

Packaged semiconductor die and CTE-engineering die pair

Single layer low cost wafer level packaging for SFF SiP

Wavy interconnect for bendable and stretchable devices

Electric circuit on flexible substrate

Solder in cavity interconnection technology

Substrate for integrated circuit devices including multi-layer glas...

Dense interconnect with solder cap (DISC) formation with laser abla...

Microelectronic package having non-coplanar, encapsulated microelec...

Integrated circuit package assemblies including a glass solder mask...

Semiconductor device with pre-molding chip bonding

Package with dielectric or anisotropic conductive (ACF) buildup layer

Solder in cavity interconnection structures

Microelectronic package having direct contact heat spreader and met...

Method apparatus and material for radio frequency passives and ante...

Substrate for integrated circuit devices including multi-layer glas...

Single layer low cost wafer level packaging for SFF SiP

Off-plane conductive line interconnects in microelectronic devices

Solder in cavity interconnection structures

Patents Applicationslast 30 patents

Integrated Circuit Packaging Method and Integrated Packaging Circuit

Integrated circuit system and packaging method therefor

Integrated Circuit Multichip Stacked Packaging Structure and Method

Integrated Circuit Packaging Method and Integrated Packaged Circuit

Chip Wiring Method and Structure

Integrated Circuit Packaging Structure and Method

PACKAGED SEMICONDUCTOR DIE AND CTE-ENGINEERING DIE PAIR

SINGLE LAYER LOW COST WAFER LEVEL PACKAGING FOR SFF SIP

SOLDER IN CAVITY INTERCONNECTION STRUCTURES

MULTI-LAYER PACKAGE

PACKAGE WITH DIELECTRIC OR ANISOTROPIC CONDUCTIVE (ACF) BUILDUP LAYER

WAVY INTERCONNECT FOR BENDABLE AND STRETCHABLE DEVICES

MAGNETIC NANOCOMPOSITE MATERIALS AND PASSIVE COMPONENTS FORMED THER...

SUBSTRATE FOR INTEGRATED CIRCUIT DEVICES INCLUDING MULTI-LAYER GLAS...

MULTI-CHIP-MODULE SEMICONDUCTOR CHIP PACKAGE HAVING DENSE PACKAGE W...

SINGLE LAYER LOW COST WAFER LEVEL PACKAGING FOR SFF SIP

SOLDER IN CAVITY INTERCONNECTION STRUCTURES

ELECTRIC CIRCUIT ON FLEXIBLE SUBSTRATE

ELECTRONIC PACKAGE AND METHOD OF FORMING AN ELECTRONIC PACKAGE

SOLDER IN CAVITY INTERCONNECTION STRUCTURES

SEMICONDUCTOR DEVICE WITH PRE-MOLDING CHIP BONDING

INTEGRATED CIRCUIT PACKAGE ASSEMBLIES INCLUDING A GLASS SOLDER MASK...

Method Apparatus and Material for Radio Frequency Passives and Ante...

SOLDER IN CAVITY INTERCONNECTION TECHNOLOGY

PACKAGE WITH DIELECTRIC OR ANISOTROPIC CONDUCTIVE (ACF) BUILDUP LAYER

SEMICONDUCTOR DEVICE WITH PRE-MOLDING CHIP BONDING

OFF-PLANE CONDUCTIVE LINE INTERCONNECTS IN MICROELECTRONIC DEVICES

MICROELECTRONIC PACKAGE HAVING NON-COPLANAR, ENCAPSULATED MICROELEC...

DENSE INTERCONNECT WITH SOLDER CAP (DISC) FORMATION WITH LASER ABLA...

PACKAGED SEMICONDUCTOR DIE AND CTE-ENGINEERING DIE PAIR