Chuen-Der Lien

Person

Los Altos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Monotonic counter memory system
- Patent number 11,901,899
- Issue date Feb 13, 2024
- Winbond Electronics Corp.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and multi physical cells error correction method thereof
- Patent number 11,314,588
- Issue date Apr 26, 2022
- Winbond Electronics Corp.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory device
- Patent number 11,114,180
- Issue date Sep 7, 2021
- Winbond Electronics Corp.
- Chi-Shun Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory apparatus and data accessing method thereof
- Patent number 11,088,711
- Issue date Aug 10, 2021
- Winbond Electronics Corp.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory storage apparatus with dynamic data repair mechanism and met...
- Patent number 11,010,245
- Issue date May 18, 2021
- Winbond Electronics Corp.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encoding method and memory storage apparatus using the same
- Patent number 11,003,529
- Issue date May 11, 2021
- Winbond Electronics Corp.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction code memory device and codeword accessing method t...
- Patent number 10,956,259
- Issue date Mar 23, 2021
- Winbond Electronics Corp.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory apparatus having hierarchical error correction code layer
- Patent number 10,853,167
- Issue date Dec 1, 2020
- Winbond Electronics Corp.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RRAM with plurality of 1TnR structures
- Patent number 10,811,092
- Issue date Oct 20, 2020
- Winbond Electronics Corp.
- Chi-Shun Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device having parameter adjusting mechanism and method of ad...
- Patent number 10,783,973
- Issue date Sep 22, 2020
- Winbond Electronics Corp.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encoding method and memory storage apparatus using the same
- Patent number 10,514,980
- Issue date Dec 24, 2019
- Winbond Electronics Corp.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encoding method and a memory storage apparatus using the same
- Patent number 10,372,535
- Issue date Aug 6, 2019
- Winbond Electronics Corp.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data read method and memory storage device using the same
- Patent number 10,348,337
- Issue date Jul 9, 2019
- Winbond Electronics Corp.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error checking and correcting decoder
- Patent number 10,236,913
- Issue date Mar 19, 2019
- Winbond Electronics Corp.
- Chuen-Der Lien
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and systems for detecting and correcting errors in nonvolat...
- Patent number 9,836,349
- Issue date Dec 5, 2017
- Winbond Electronics Corp.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems for nonvolatile memory data management
- Patent number 9,720,771
- Issue date Aug 1, 2017
- Winbond Electronics Corp.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems for nonvolatile memory data management
- Patent number 9,563,505
- Issue date Feb 7, 2017
- Winbond Electronics Corp.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Look-ahead built-in self tests with temperature elevation of functi...
- Patent number 8,028,211
- Issue date Sep 27, 2011
- Integrated Device Technology, Inc.
- Michael Miller
- G01 - MEASURING TESTING
Information Patent Grant
Clock generator and method for providing reliable clock signal usin...
- Patent number 7,941,723
- Issue date May 10, 2011
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G01 - MEASURING TESTING
Information Patent Grant
Method for forming integrated circuit device using cell library wit...
- Patent number 7,921,400
- Issue date Apr 5, 2011
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look-ahead built-in self tests
- Patent number 7,877,657
- Issue date Jan 25, 2011
- Integrated Device Technology, Inc.
- Michael Miller
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for CAM with reduced cross-coupling interference
- Patent number 7,859,876
- Issue date Dec 28, 2010
- Netlogic Microsystems, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
CAM arrays having CAM cells therein with match line and low match l...
- Patent number RE41351
- Issue date May 25, 2010
- NetLogic Microsystems, Inc.
- Chuen-Der Lien
- 365 - Static information storage and retrieval
Information Patent Grant
Electrical overstress (EOS) and electrostatic discharge (ESD) prote...
- Patent number 7,706,113
- Issue date Apr 27, 2010
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Logic soft error rate prediction and improvement
- Patent number 7,644,311
- Issue date Jan 5, 2010
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for clock generation
- Patent number 7,602,226
- Issue date Oct 13, 2009
- Integrated Device Technology, Inc.
- Frank Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for forming CMOS device with self-aligned contacts and regio...
- Patent number 7,582,567
- Issue date Sep 1, 2009
- Integrated Device Technology, Inc.
- Tsengyou Syau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die seal with reduced noise coupling
- Patent number 7,560,800
- Issue date Jul 14, 2009
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for CAM with reduced cross-coupling interference
- Patent number 7,545,660
- Issue date Jun 9, 2009
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for CAM with reduced cross-coupling interference
- Patent number 7,522,438
- Issue date Apr 21, 2009
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MONOTONIC COUNTER MEMORY SYSTEM
- Publication number 20220345135
- Publication date Oct 27, 2022
- WINBOND ELECTRONICS CORP.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE AND MULTI PHYSICAL CELLS ERROR CORRECTION METHOD THEREOF
- Publication number 20210141689
- Publication date May 13, 2021
- WINBOND ELECTRONICS CORP.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY APPARATUS AND DATA ACCESSING METHOD THEREOF
- Publication number 20210013906
- Publication date Jan 14, 2021
- WINBOND ELECTRONICS CORP.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY APPARATUS HAVING HIERARCHICAL ERROR CORRECTION CODE LAYER
- Publication number 20200241957
- Publication date Jul 30, 2020
- WINBOND ELECTRONICS CORP.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTION CODE MEMORY DEVICE AND CODEWORD ACCESSING METHOD T...
- Publication number 20200233743
- Publication date Jul 23, 2020
- WINBOND ELECTRONICS CORP.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY STORAGE APPARATUS WITH DYNAMIC DATA REPAIR MECHANISM AND MET...
- Publication number 20190391874
- Publication date Dec 26, 2019
- WINBOND ELECTRONICS CORP.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENCODING METHOD AND MEMORY STORAGE APPARATUS USING THE SAME
- Publication number 20190340070
- Publication date Nov 7, 2019
- WINBOND ELECTRONICS CORP.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENCODING METHOD AND MEMORY STORAGE APPARATUS USING THE SAME
- Publication number 20190294496
- Publication date Sep 26, 2019
- WINBOND ELECTRONICS CORP.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF IMPLEMENTING ERROR CORRECTION CODE USED BY MEMORY STORAGE...
- Publication number 20190294497
- Publication date Sep 26, 2019
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENCODING METHOD AND A MEMORY STORAGE APPARATUS USING THE SAME
- Publication number 20190065307
- Publication date Feb 28, 2019
- WINBOND ELECTRONICS CORP.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CHECKING AND CORRECTING DECODER
- Publication number 20180331700
- Publication date Nov 15, 2018
- WINBOND ELECTRONICS CORP.
- Chuen-Der Lien
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DATA READ METHOD AND MEMORY STORAGE DEVICE USING THE SAME
- Publication number 20180239533
- Publication date Aug 23, 2018
- WINBOND ELECTRONICS CORP.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR NONVOLATILE MEMORY DATA MANAGEMENT
- Publication number 20170102994
- Publication date Apr 13, 2017
- WINBOND ELECTRONICS CORP.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR NONVOLATILE MEMORY DATA MANAGEMENT
- Publication number 20160350183
- Publication date Dec 1, 2016
- WINBOND ELECTRONICS CORP.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR DETECTING AND CORRECTING ERRORS IN NONVOLAT...
- Publication number 20160350178
- Publication date Dec 1, 2016
- WINBOND ELECTRONICS CORP.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for improved single event latch up resistance in an integrat...
- Publication number 20080122473
- Publication date May 29, 2008
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Logic soft error rate prediction and improvement
- Publication number 20070234125
- Publication date Oct 4, 2007
- Chuen-Der Lien
- G01 - MEASURING TESTING
Information Patent Application
Dual port memory cell with reduced coupling capacitance and small c...
- Publication number 20060227649
- Publication date Oct 12, 2006
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Application
Binary and ternary non-volatile CAM
- Publication number 20060067097
- Publication date Mar 30, 2006
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Application
Memory array bit line coupling capacitor cancellation
- Publication number 20060028860
- Publication date Feb 9, 2006
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Application
CAM circuit with radiation resistance
- Publication number 20040208034
- Publication date Oct 21, 2004
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Application
FIFO memory devices having multi-port cache memory arrays therein t...
- Publication number 20040047209
- Publication date Mar 11, 2004
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Application
FIFO memory devices having multi-port cache memory arrays therein t...
- Publication number 20040019743
- Publication date Jan 29, 2004
- Mario Au
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CAM CIRCUIT WITH SEPARATE MEMORY AND LOGIC OPERATING VOLTAGES
- Publication number 20030227789
- Publication date Dec 11, 2003
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Application
CAM circuit with radiation resistance
- Publication number 20030227788
- Publication date Dec 11, 2003
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Application
Content addressable memory (CAM) devices having reliable column red...
- Publication number 20030165073
- Publication date Sep 4, 2003
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Application
Cam circuit with error correction
- Publication number 20030007408
- Publication date Jan 9, 2003
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Application
CAM circuit with radiation resistance
- Publication number 20020159320
- Publication date Oct 31, 2002
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE
Information Patent Application
ESD protection circuit
- Publication number 20020131221
- Publication date Sep 19, 2002
- Chuen-Der Lien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor integrated circuit with an insulation structure havin...
- Publication number 20010040267
- Publication date Nov 15, 2001
- Chuen-Der Lien
- H01 - BASIC ELECTRIC ELEMENTS

Chuen-Der Lien

Person

Patents Grantslast 30 patents

Monotonic counter memory system

Memory device and multi physical cells error correction method thereof

Non-volatile memory device

Memory apparatus and data accessing method thereof

Memory storage apparatus with dynamic data repair mechanism and met...

Encoding method and memory storage apparatus using the same

Error correction code memory device and codeword accessing method t...

Memory apparatus having hierarchical error correction code layer

RRAM with plurality of 1TnR structures

Memory device having parameter adjusting mechanism and method of ad...

Encoding method and memory storage apparatus using the same

Encoding method and a memory storage apparatus using the same

Data read method and memory storage device using the same

Error checking and correcting decoder

Methods and systems for detecting and correcting errors in nonvolat...

Methods and systems for nonvolatile memory data management

Methods and systems for nonvolatile memory data management

Look-ahead built-in self tests with temperature elevation of functi...

Clock generator and method for providing reliable clock signal usin...

Method for forming integrated circuit device using cell library wit...

Look-ahead built-in self tests

Method and apparatus for CAM with reduced cross-coupling interference

CAM arrays having CAM cells therein with match line and low match l...

Electrical overstress (EOS) and electrostatic discharge (ESD) prote...

Logic soft error rate prediction and improvement

Method and apparatus for clock generation

Method for forming CMOS device with self-aligned contacts and regio...

Die seal with reduced noise coupling

Method and apparatus for CAM with reduced cross-coupling interference

Method and apparatus for CAM with reduced cross-coupling interference

Patents Applicationslast 30 patents

MONOTONIC COUNTER MEMORY SYSTEM

MEMORY DEVICE AND MULTI PHYSICAL CELLS ERROR CORRECTION METHOD THEREOF

MEMORY APPARATUS AND DATA ACCESSING METHOD THEREOF

MEMORY APPARATUS HAVING HIERARCHICAL ERROR CORRECTION CODE LAYER

ERROR CORRECTION CODE MEMORY DEVICE AND CODEWORD ACCESSING METHOD T...

MEMORY STORAGE APPARATUS WITH DYNAMIC DATA REPAIR MECHANISM AND MET...

ENCODING METHOD AND MEMORY STORAGE APPARATUS USING THE SAME

ENCODING METHOD AND MEMORY STORAGE APPARATUS USING THE SAME

METHOD OF IMPLEMENTING ERROR CORRECTION CODE USED BY MEMORY STORAGE...

ENCODING METHOD AND A MEMORY STORAGE APPARATUS USING THE SAME

ERROR CHECKING AND CORRECTING DECODER

DATA READ METHOD AND MEMORY STORAGE DEVICE USING THE SAME

METHODS AND SYSTEMS FOR NONVOLATILE MEMORY DATA MANAGEMENT

METHODS AND SYSTEMS FOR NONVOLATILE MEMORY DATA MANAGEMENT

METHODS AND SYSTEMS FOR DETECTING AND CORRECTING ERRORS IN NONVOLAT...

Method for improved single event latch up resistance in an integrat...

Logic soft error rate prediction and improvement

Dual port memory cell with reduced coupling capacitance and small c...

Binary and ternary non-volatile CAM

Memory array bit line coupling capacitor cancellation

CAM circuit with radiation resistance

FIFO memory devices having multi-port cache memory arrays therein t...

FIFO memory devices having multi-port cache memory arrays therein t...

CAM CIRCUIT WITH SEPARATE MEMORY AND LOGIC OPERATING VOLTAGES

CAM circuit with radiation resistance

Content addressable memory (CAM) devices having reliable column red...

Cam circuit with error correction

CAM circuit with radiation resistance

ESD protection circuit

Semiconductor integrated circuit with an insulation structure havin...