Chulmin Jung

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory with bitcell power boosting
- Patent number 12,125,526
- Issue date Oct 22, 2024
- QUALCOMM Incorporated
- Chulmin Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with double redundancy
- Patent number 12,094,528
- Issue date Sep 17, 2024
- QUALCOMM Incorporated
- Dhvani Sheth
- G11 - INFORMATION STORAGE
Information Patent Grant
Power supply circuit with reduced leakage current
- Patent number 12,047,073
- Issue date Jul 23, 2024
- QUALCOMM Incorporated
- Pradeep Raj
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of pseudo-triple-port SRAM datapaths
- Patent number 12,014,771
- Issue date Jun 18, 2024
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with scan chain testing of column redundancy logic and multi...
- Patent number 11,935,606
- Issue date Mar 19, 2024
- QUALCOMM Incorporated
- Rahul Sahu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with a sense amplifier isolation scheme for enhancing memory...
- Patent number 11,894,050
- Issue date Feb 6, 2024
- QUALCOMM Incorporated
- Hochul Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with efficient DVS controlled by asynchronous inputs
- Patent number 11,837,313
- Issue date Dec 5, 2023
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with single-ended sensing using reset-set latch
- Patent number 11,670,351
- Issue date Jun 6, 2023
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-dual-port SRAM with burst-mode address comparator
- Patent number 11,640,838
- Issue date May 2, 2023
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-triple-port SRAM datapaths
- Patent number 11,615,837
- Issue date Mar 28, 2023
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-leakage drain-programmed ROM
- Patent number 11,610,633
- Issue date Mar 21, 2023
- Qualcomm, Incorporated
- Xiao Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with burst mode operation
- Patent number 11,527,282
- Issue date Dec 13, 2022
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Write assist scheme with bitline
- Patent number 11,488,658
- Issue date Nov 1, 2022
- QUALCOMM Incorporated
- Chulmin Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Burst-mode memory with column multiplexer
- Patent number 11,462,263
- Issue date Oct 4, 2022
- QUALCOMM Incorporated
- Changho Jung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory write methods and circuits
- Patent number 11,450,359
- Issue date Sep 20, 2022
- QUALCOMM Incorporated
- Xiao Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-triple-port SRAM bitcell architecture
- Patent number 11,361,817
- Issue date Jun 14, 2022
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for driving wordlines using set-reset latches
- Patent number 11,250,895
- Issue date Feb 15, 2022
- QUALCOMM Incorporated
- Dhvani Sheth
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for reducing rock bottom leakage in memory
- Patent number 11,170,845
- Issue date Nov 9, 2021
- QUALCOMM Incorporated
- Arun Babu Pallerla
- G11 - INFORMATION STORAGE
Information Patent Grant
Area-efficient dynamic memory redundancy scheme with priority decoding
- Patent number 11,170,865
- Issue date Nov 9, 2021
- QUALCOMM Incorporated
- Chulmin Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Determining a voltage and/or frequency for a performance mode
- Patent number 11,092,646
- Issue date Aug 17, 2021
- QUALCOMM Incorporated
- Sonia Ghosh
- G01 - MEASURING TESTING
Information Patent Grant
Write assist circuitry for memory
- Patent number 11,049,552
- Issue date Jun 29, 2021
- QUALCOMM Incorporated
- Pradeep Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with burst mode operation
- Patent number 10,923,185
- Issue date Feb 16, 2021
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Asymmetric memory tag access and design
- Patent number 10,831,667
- Issue date Nov 10, 2020
- QUALCOMM Incorporated
- Bharat Kumar Rangarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read tracking scheme for a memory device
- Patent number 10,796,735
- Issue date Oct 6, 2020
- QUALCOMM Incorporated
- Hochul Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM with burst mode address comparator
- Patent number 10,770,132
- Issue date Sep 8, 2020
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Byte enable memory built-in self-test (MBIST) algorithm
- Patent number 10,748,641
- Issue date Aug 18, 2020
- QUALCOMM Incorporated
- Greg Seok
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory repair enablement
- Patent number 10,713,136
- Issue date Jul 14, 2020
- QUALCOMM Incorporated
- Fahad Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write driver scheme for bit-writable memories
- Patent number 10,325,648
- Issue date Jun 18, 2019
- QUALCOMM Incorporated
- Darshit Mehta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage droop control
- Patent number 10,133,285
- Issue date Nov 20, 2018
- QUALCOMM Incorporated
- Sanjay Bhagawan Patil
- G05 - CONTROLLING REGULATING
Information Patent Grant
Flexible memory assistance scheme
- Patent number 10,049,729
- Issue date Aug 14, 2018
- QUALCOMM Incorporated
- Esin Terzioglu
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
High-Speed and Area-Efficient Parallel-Write-and-Read Memory
- Publication number 20250022494
- Publication date Jan 16, 2025
- QUALCOMM Incorporated
- Hochul LEE
- G11 - INFORMATION STORAGE
Information Patent Application
POWER MULTIPLEXER
- Publication number 20240429908
- Publication date Dec 26, 2024
- QUALCOMM Incorporated
- Harshat PANT
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY WITH DOUBLE REDUNDANCY
- Publication number 20240395320
- Publication date Nov 28, 2024
- QUALCOMM Incorporated
- Dhvani SHETH
- G11 - INFORMATION STORAGE
Information Patent Application
Power Level Comparator with Switching Input
- Publication number 20240355381
- Publication date Oct 24, 2024
- QUALCOMM Incorporated
- Seohee KIM
- G11 - INFORMATION STORAGE
Information Patent Application
Pseudo-Differential De-Glitch Sense Amplifier
- Publication number 20240257868
- Publication date Aug 1, 2024
- QUALCOMM Incorporated
- Chulmin JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with Scan Chain Testing of Column Redundancy Logic and Multi...
- Publication number 20240221853
- Publication date Jul 4, 2024
- QUALCOMM Incorporated
- Rahul SAHU
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH DOUBLE REDUNDANCY
- Publication number 20230395139
- Publication date Dec 7, 2023
- QUALCOMM Incorporated
- Dhvani SHETH
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with Bitcell Power Boosting
- Publication number 20230317150
- Publication date Oct 5, 2023
- QUALCOMM Incorporated
- Chulmin JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO-TRIPLE-PORT SRAM DATAPATHS
- Publication number 20230223075
- Publication date Jul 13, 2023
- QUALCOMM Incorporated
- Changho JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
POWER SUPPLY CIRCUIT WITH REDUCED LEAKAGE CURRENT
- Publication number 20230179183
- Publication date Jun 8, 2023
- QUALCOMM Incorporated
- Pradeep RAJ
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory with Single-Ended Sensing Using Reset-Set Latch
- Publication number 20230170000
- Publication date Jun 1, 2023
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH EFFICIENT DVS CONTROLLED BY ASYNCHRONOUS INPUTS
- Publication number 20230139283
- Publication date May 4, 2023
- QUALCOMM Incorporated
- Pradeep RAJ
- G11 - INFORMATION STORAGE
Information Patent Application
PSEUDO-DUAL-PORT SRAM WITH BURST-MODE ADDRESS COMPARATOR
- Publication number 20230093852
- Publication date Mar 30, 2023
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH A SENSE AMPLIFIER ISOLATION SCHEME FOR ENHANCING MEMORY...
- Publication number 20230087277
- Publication date Mar 23, 2023
- QUALCOMM Incorporated
- Hochul LEE
- G11 - INFORMATION STORAGE
Information Patent Application
LOW-LEAKAGE DRAIN-PROGRAMMED ROM
- Publication number 20230005546
- Publication date Jan 5, 2023
- QUALCOMM Incorporated
- Xiao CHEN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH SCAN CHAIN TESTING OF COLUMN REDUNDANCY LOGIC AND MULTI...
- Publication number 20230005556
- Publication date Jan 5, 2023
- QUALCOMM Incorporated
- Rahul SAHU
- G11 - INFORMATION STORAGE
Information Patent Application
BURST-MODE MEMORY WITH COLUMN MULTIPLEXER
- Publication number 20220199152
- Publication date Jun 23, 2022
- QUALCOMM Incorporated
- Changho JUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PSEUDO-TRIPLE-PORT SRAM DATAPATHS
- Publication number 20220093171
- Publication date Mar 24, 2022
- QUALCOMM Incorporated
- Changho JUNG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PSEUDO-TRIPLE-PORT SRAM BITCELL ARCHITECTURE
- Publication number 20220068360
- Publication date Mar 3, 2022
- QUALCOMM Incorporated
- Arun Babu PALLERLA
- G11 - INFORMATION STORAGE
Information Patent Application
AREA-EFFICIENT DYNAMIC MEMORY REDUNDANCY SCHEME WITH PRIORITY DECODING
- Publication number 20210350865
- Publication date Nov 11, 2021
- QUALCOMM Incorporated
- Chulmin Jung
- G11 - INFORMATION STORAGE
Information Patent Application
Write Assist Scheme with Bitline
- Publication number 20210343330
- Publication date Nov 4, 2021
- QUALCOMM Incorporated
- Chulmin Jung
- G11 - INFORMATION STORAGE
Information Patent Application
DETERMINING A VOLTAGE AND/OR FREQUENCY FOR A PERFORMANCE MODE
- Publication number 20210255243
- Publication date Aug 19, 2021
- QUALCOMM Incorporated
- Sonia GHOSH
- G01 - MEASURING TESTING
Information Patent Application
SRAM WITH BURST MODE OPERATION
- Publication number 20210134358
- Publication date May 6, 2021
- Qualcomm Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM LOW-POWER WRITE DRIVER
- Publication number 20210098057
- Publication date Apr 1, 2021
- QUALCOMM Incorporated
- Changho JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WITH BURST MODE OPERATION
- Publication number 20200388328
- Publication date Dec 10, 2020
- QUALCOMM Incorporated
- Changho Jung
- G11 - INFORMATION STORAGE
Information Patent Application
PHYSICALLY UNCLONABLE FUNCTION (PUF) IN PROGRAMMABLE READ-ONLY MEMO...
- Publication number 20200365222
- Publication date Nov 19, 2020
- QUALCOMM Incorporated
- Hochul LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER MEMORY
- Publication number 20200335151
- Publication date Oct 22, 2020
- QUALCOMM Incorporated
- Chulmin JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
ASYMMETRIC MEMORY TAG ACCESS AND DESIGN
- Publication number 20200133862
- Publication date Apr 30, 2020
- QUALCOMM Incorporated
- Bharat Kumar RANGARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BYTE ENABLE MEMORY BUILT-IN SELF-TEST (MBIST) ALGORITHM
- Publication number 20190115091
- Publication date Apr 18, 2019
- QUALCOMM Incorporated
- Greg Seok
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY REPAIR ENABLEMENT
- Publication number 20190095295
- Publication date Mar 28, 2019
- QUALCOMM Incorporated
- Fahad AHMED
- G06 - COMPUTING CALCULATING COUNTING

Chulmin Jung

Person

Patents Grantslast 30 patents

Memory with bitcell power boosting

Memory with double redundancy

Power supply circuit with reduced leakage current

Method of pseudo-triple-port SRAM datapaths

Memory with scan chain testing of column redundancy logic and multi...

Memory with a sense amplifier isolation scheme for enhancing memory...

Memory with efficient DVS controlled by asynchronous inputs

Memory with single-ended sensing using reset-set latch

Pseudo-dual-port SRAM with burst-mode address comparator

Pseudo-triple-port SRAM datapaths

Low-leakage drain-programmed ROM

SRAM with burst mode operation

Write assist scheme with bitline

Burst-mode memory with column multiplexer

Memory write methods and circuits

Pseudo-triple-port SRAM bitcell architecture

Systems and methods for driving wordlines using set-reset latches

Techniques for reducing rock bottom leakage in memory

Area-efficient dynamic memory redundancy scheme with priority decoding

Determining a voltage and/or frequency for a performance mode

Write assist circuitry for memory

SRAM with burst mode operation

Asymmetric memory tag access and design

Read tracking scheme for a memory device

SRAM with burst mode address comparator

Byte enable memory built-in self-test (MBIST) algorithm

Memory repair enablement

Write driver scheme for bit-writable memories

Voltage droop control

Flexible memory assistance scheme

Patents Applicationslast 30 patents

High-Speed and Area-Efficient Parallel-Write-and-Read Memory

POWER MULTIPLEXER

MEMORY WITH DOUBLE REDUNDANCY

Power Level Comparator with Switching Input

Pseudo-Differential De-Glitch Sense Amplifier

Memory with Scan Chain Testing of Column Redundancy Logic and Multi...

MEMORY WITH DOUBLE REDUNDANCY

Memory with Bitcell Power Boosting

PSEUDO-TRIPLE-PORT SRAM DATAPATHS

POWER SUPPLY CIRCUIT WITH REDUCED LEAKAGE CURRENT

Memory with Single-Ended Sensing Using Reset-Set Latch

MEMORY WITH EFFICIENT DVS CONTROLLED BY ASYNCHRONOUS INPUTS

PSEUDO-DUAL-PORT SRAM WITH BURST-MODE ADDRESS COMPARATOR

MEMORY WITH A SENSE AMPLIFIER ISOLATION SCHEME FOR ENHANCING MEMORY...

LOW-LEAKAGE DRAIN-PROGRAMMED ROM

MEMORY WITH SCAN CHAIN TESTING OF COLUMN REDUNDANCY LOGIC AND MULTI...

BURST-MODE MEMORY WITH COLUMN MULTIPLEXER

PSEUDO-TRIPLE-PORT SRAM DATAPATHS

PSEUDO-TRIPLE-PORT SRAM BITCELL ARCHITECTURE

AREA-EFFICIENT DYNAMIC MEMORY REDUNDANCY SCHEME WITH PRIORITY DECODING

Write Assist Scheme with Bitline

DETERMINING A VOLTAGE AND/OR FREQUENCY FOR A PERFORMANCE MODE

SRAM WITH BURST MODE OPERATION

SRAM LOW-POWER WRITE DRIVER

SRAM WITH BURST MODE OPERATION

PHYSICALLY UNCLONABLE FUNCTION (PUF) IN PROGRAMMABLE READ-ONLY MEMO...

LOW-POWER MEMORY

ASYMMETRIC MEMORY TAG ACCESS AND DESIGN

BYTE ENABLE MEMORY BUILT-IN SELF-TEST (MBIST) ALGORITHM

MEMORY REPAIR ENABLEMENT