Chung-Chi Wang

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for decoding error correcting codes
- Patent number 11,115,051
- Issue date Sep 7, 2021
- INNOGRIT TECHNOLOGIES CO., LTD.
- Yuan-mao Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sequence to sequence to classification model for generating recomme...
- Patent number 10,721,190
- Issue date Jul 21, 2020
- Microsoft Technology Licensing, LLC
- Bing Zhao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for decoding error correcting codes with self-g...
- Patent number 10,715,182
- Issue date Jul 14, 2020
- INNOGRIT TECHNOLOGIES CO., LTD.
- Jie Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for decoding error correcting codes
- Patent number 10,574,274
- Issue date Feb 25, 2020
- Nyquist Semiconductor Limited
- Yuan-mao Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for decoding error correcting codes
- Patent number 10,511,326
- Issue date Dec 17, 2019
- Nyquist Semiconductor Limited
- Yuan-mao Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for decoding error correcting codes
- Patent number 10,491,244
- Issue date Nov 26, 2019
- Nyquist Semiconductor Limited
- Yuan-mao Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Shared mesh
- Patent number 10,193,826
- Issue date Jan 29, 2019
- Intel Corporation
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient encoder based on modified RU algorithm
- Patent number 10,141,072
- Issue date Nov 27, 2018
- SK Hynix Inc.
- Wei-Hao Yuan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reliability-assisted bit-flipping decoding algorithm
- Patent number 10,135,464
- Issue date Nov 20, 2018
- SK Hynix Inc.
- Chung-Li Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cyclically interleaved XOR array for error recovery
- Patent number 9,996,285
- Issue date Jun 12, 2018
- SK Hynix Inc.
- Jingyu Kang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
One-shot decoder for two-error-correcting BCH codes
- Patent number 9,906,240
- Issue date Feb 27, 2018
- SK Hynix Inc.
- Yi-Min Lin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for adaptive LDPC decoding
- Patent number 9,866,241
- Issue date Jan 9, 2018
- SK Hynix Inc.
- Johnson Yen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Encoder by-pass with scrambler
- Patent number 9,710,326
- Issue date Jul 18, 2017
- SK Hynix Inc.
- Fan Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for local iteration randomization in a data dec...
- Patent number 9,324,372
- Issue date Apr 26, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Fan Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for check-node unit message processing
- Patent number 9,244,685
- Issue date Jan 26, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Zongwang Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for skip layer data decoding
- Patent number 9,214,959
- Issue date Dec 15, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Shaohua Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-binary layered low density parity check decoder
- Patent number 9,130,590
- Issue date Sep 8, 2015
- LSI Corporation
- Dan Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Low density parity check decoder with dynamic scaling
- Patent number 9,130,589
- Issue date Sep 8, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Shu Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for gate aware iterative data processing
- Patent number 9,058,842
- Issue date Jun 16, 2015
- LSI Corporation
- Fan Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for multi-stage encoding of concatenated low de...
- Patent number 9,048,873
- Issue date Jun 2, 2015
- LSI Corporation
- Zongwang Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Shift register-based layered low density parity check decoder
- Patent number 9,048,867
- Issue date Jun 2, 2015
- LSI Corporation
- Dan Liu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Min-sum based hybrid non-binary low density parity check decoder
- Patent number 9,048,874
- Issue date Jun 2, 2015
- LSI Corporation
- Chung-Li Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory architecture for layered low-density parity-check decoder
- Patent number 9,037,952
- Issue date May 19, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Zongwang Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hardware architecture and implementation of low power layered multi...
- Patent number 9,037,938
- Issue date May 19, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Lei Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-level LDPC layered decoder with out-of-order processing
- Patent number 9,015,547
- Issue date Apr 21, 2015
- LSI Corporation
- Chung-Li Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Low density parity check layer decoder for codes with overlapped ci...
- Patent number 9,015,550
- Issue date Apr 21, 2015
- LSI Corporation
- Chung-Li Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
1T MIM memory for embedded RAM application in soc
- Patent number 9,012,967
- Issue date Apr 21, 2015
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Ching Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for reusing a layered decoder to yield a non-la...
- Patent number 9,009,557
- Issue date Apr 14, 2015
- LSI Corporation
- Shu Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for compression driven variable rate decoding i...
- Patent number 8,977,937
- Issue date Mar 10, 2015
- LSI Corporation
- Fan Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Modified targeted symbol flipping for non-binary LDPC codes
- Patent number 8,977,926
- Issue date Mar 10, 2015
- LSI Corporation
- Chung-Li Wang
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
ON-PACKAGE ACCELERATOR COMPLEX (AC) FOR INTEGRATING ACCELERATOR AND...
- Publication number 20220222194
- Publication date Jul 14, 2022
- Intel Corporation
- Neelam CHANDWANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems, Apparatus And Methods For Rapid Peripheral Component Inter...
- Publication number 20210294772
- Publication date Sep 23, 2021
- Intel Corporation
- Amit Kumar Srivastava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR DECODING ERROR CORRECTING CODES
- Publication number 20200059243
- Publication date Feb 20, 2020
- Nyquist Semiconductor Limited
- Yuan-mao Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEQUENCE TO SEQUENCE TO CLASSIFICATION MODEL FOR GENERATING RECOMME...
- Publication number 20200044990
- Publication date Feb 6, 2020
- Microsoft Technology Licensing, LLC
- Bing Zhao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR DECODING ERROR CORRECTING CODES WITH SELF-G...
- Publication number 20200036395
- Publication date Jan 30, 2020
- Nyquist Semiconductor Limited
- Jie Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR DECODING ERROR CORRECTING CODES
- Publication number 20190149168
- Publication date May 16, 2019
- Nyquist Semiconductor Limited
- Yuan-mao Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR DECODING ERROR CORRECTING CODES
- Publication number 20190149169
- Publication date May 16, 2019
- Nyquist Semiconductor Limited
- Yuan-mao Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR DECODING ERROR CORRECTING CODES
- Publication number 20190103885
- Publication date Apr 4, 2019
- Nyquist Semiconductor Limited
- Yuan-mao Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CYCLICALLY INTERLEAVED XOR ARRAY FOR ERROR RECOVERY
- Publication number 20180129430
- Publication date May 10, 2018
- SK HYNIX MEMORY SOLUTIONS INC.
- Jingyu Kang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR ADAPTIVE LDPC DECODING
- Publication number 20170093428
- Publication date Mar 30, 2017
- SK HYNIX INC.
- Johnson Yen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SHARED MESH
- Publication number 20170019350
- Publication date Jan 19, 2017
- Intel Corporation
- Bahaa Fahim
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
EFFICIENT ENCODER BASED ON MODIFIED RU ALGORITHM
- Publication number 20160364292
- Publication date Dec 15, 2016
- SK HYNIX MEMORY SOLUTIONS INC.
- Wei-Hao YUAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ONE-SHOT DECODER FOR TWO-ERROR-CORRECTING BCH CODES
- Publication number 20160359502
- Publication date Dec 8, 2016
- SK HYNIX MEMORY SOLUTIONS INC.
- Yi-Min LIN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RELIABILITY-ASSISTED BIT-FLIPPING DECODING ALGORITHM
- Publication number 20160197624
- Publication date Jul 7, 2016
- SK HYNIX MEMORY SOLUTIONS INC.
- Chung-Li Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ENCODER BY-PASS WITH SCRAMBLER
- Publication number 20160026526
- Publication date Jan 28, 2016
- SK HYNIX MEMORY SOLUTIONS INC.
- Fan Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Non-Binary Layered Low Density Parity Check Decoder
- Publication number 20150092290
- Publication date Apr 2, 2015
- LSI Corporation
- Dan Liu
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods for Hybrid Layer Data Decoding
- Publication number 20140372828
- Publication date Dec 18, 2014
- Shu Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Shift Register-Based Layered Low Density Parity Check Decoder
- Publication number 20140351671
- Publication date Nov 27, 2014
- LSI Corporation
- Dan Liu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Min-Sum Based Hybrid Non-Binary Low Density Parity Check Decoder
- Publication number 20140281787
- Publication date Sep 18, 2014
- LSI Corporation
- Chung-Li Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Systems and Methods for Multi-Stage Encoding Of Concatenated Low De...
- Publication number 20140281790
- Publication date Sep 18, 2014
- Zongwang Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Systems and Methods for Skip Layer Data Decoding
- Publication number 20140237314
- Publication date Aug 21, 2014
- LSI Corporation
- Shaohua Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods for Trapping Set Disruption
- Publication number 20140237313
- Publication date Aug 21, 2014
- LSI Corporation
- Chung-Li Wang
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and Methods for Shared Layer Data Decoding
- Publication number 20140226229
- Publication date Aug 14, 2014
- LSI Corporation
- Shaohua Yang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory Architecture for Layered Low-Density Parity-Check Decoder
- Publication number 20140223259
- Publication date Aug 7, 2014
- LSI Corporation
- Zongwang Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods for Reusing a Layered Decoder to Yield a Non-La...
- Publication number 20140208180
- Publication date Jul 24, 2014
- LSI Corporation
- Shu Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Irregular Low Density Parity Check Decoder With Low Syndrome Error...
- Publication number 20140168811
- Publication date Jun 19, 2014
- LSI Corporation
- Shaohua Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Low Density Parity Check Decoder With Dynamic Scaling
- Publication number 20140173385
- Publication date Jun 19, 2014
- LSI Corporation
- Shu Li
- G11 - INFORMATION STORAGE
Information Patent Application
System and Method for Check-Node Unit Message Processing
- Publication number 20140130061
- Publication date May 8, 2014
- LSI CORPORATION
- Zongwang Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hardware Architecture and Implementation of Low Power Layered Multi...
- Publication number 20140122979
- Publication date May 1, 2014
- LSI Corporation
- Lei Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Low Density Parity Check Layer Decoder For Codes With Overlapped Ci...
- Publication number 20140101510
- Publication date Apr 10, 2014
- LSI Corporation
- Chung-Li Wang
- H03 - BASIC ELECTRONIC CIRCUITRY

Chung-Chi Wang

Person

Patents Grantslast 30 patents

Systems and methods for decoding error correcting codes

Sequence to sequence to classification model for generating recomme...

Systems and methods for decoding error correcting codes with self-g...

Systems and methods for decoding error correcting codes

Systems and methods for decoding error correcting codes

Systems and methods for decoding error correcting codes

Shared mesh

Efficient encoder based on modified RU algorithm

Reliability-assisted bit-flipping decoding algorithm

Cyclically interleaved XOR array for error recovery

One-shot decoder for two-error-correcting BCH codes

Techniques for adaptive LDPC decoding

Encoder by-pass with scrambler

Systems and methods for local iteration randomization in a data dec...

System and method for check-node unit message processing

Systems and methods for skip layer data decoding

Non-binary layered low density parity check decoder

Low density parity check decoder with dynamic scaling

Systems and methods for gate aware iterative data processing

Systems and methods for multi-stage encoding of concatenated low de...

Shift register-based layered low density parity check decoder

Min-sum based hybrid non-binary low density parity check decoder

Memory architecture for layered low-density parity-check decoder

Hardware architecture and implementation of low power layered multi...

Multi-level LDPC layered decoder with out-of-order processing

Low density parity check layer decoder for codes with overlapped ci...

1T MIM memory for embedded RAM application in soc

Systems and methods for reusing a layered decoder to yield a non-la...

Systems and methods for compression driven variable rate decoding i...

Modified targeted symbol flipping for non-binary LDPC codes

Patents Applicationslast 30 patents

ON-PACKAGE ACCELERATOR COMPLEX (AC) FOR INTEGRATING ACCELERATOR AND...

Systems, Apparatus And Methods For Rapid Peripheral Component Inter...

SYSTEMS AND METHODS FOR DECODING ERROR CORRECTING CODES

SEQUENCE TO SEQUENCE TO CLASSIFICATION MODEL FOR GENERATING RECOMME...

SYSTEMS AND METHODS FOR DECODING ERROR CORRECTING CODES WITH SELF-G...

SYSTEMS AND METHODS FOR DECODING ERROR CORRECTING CODES

SYSTEMS AND METHODS FOR DECODING ERROR CORRECTING CODES

SYSTEMS AND METHODS FOR DECODING ERROR CORRECTING CODES

CYCLICALLY INTERLEAVED XOR ARRAY FOR ERROR RECOVERY

TECHNIQUES FOR ADAPTIVE LDPC DECODING

SHARED MESH

EFFICIENT ENCODER BASED ON MODIFIED RU ALGORITHM

ONE-SHOT DECODER FOR TWO-ERROR-CORRECTING BCH CODES

RELIABILITY-ASSISTED BIT-FLIPPING DECODING ALGORITHM

ENCODER BY-PASS WITH SCRAMBLER

Non-Binary Layered Low Density Parity Check Decoder

Systems and Methods for Hybrid Layer Data Decoding

Shift Register-Based Layered Low Density Parity Check Decoder

Min-Sum Based Hybrid Non-Binary Low Density Parity Check Decoder

Systems and Methods for Multi-Stage Encoding Of Concatenated Low De...

Systems and Methods for Skip Layer Data Decoding

Systems and Methods for Trapping Set Disruption

Systems and Methods for Shared Layer Data Decoding

Memory Architecture for Layered Low-Density Parity-Check Decoder

Systems and Methods for Reusing a Layered Decoder to Yield a Non-La...

Irregular Low Density Parity Check Decoder With Low Syndrome Error...

Low Density Parity Check Decoder With Dynamic Scaling

System and Method for Check-Node Unit Message Processing

Hardware Architecture and Implementation of Low Power Layered Multi...

Low Density Parity Check Layer Decoder For Codes With Overlapped Ci...