CHUNG-LUN CHAN

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Resolving memory accesses crossing cache line boundaries
- Patent number 10,318,427
- Issue date Jun 11, 2019
- Intel Corporation
- Ramon Matas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sequencing with coherent and non-coherent sub-systems
- Patent number 10,261,904
- Issue date Apr 16, 2019
- Intel Corporation
- Chunhui Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses, methods, and systems to share translation lookaside bu...
- Patent number 10,108,554
- Issue date Oct 23, 2018
- Intel Corporation
- Chung-Lun Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing an efficient scatter
- Patent number 9,891,914
- Issue date Feb 13, 2018
- Intel Corporation
- Ramon Matas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable event handling in multi-threaded processor cores
- Patent number 9,886,396
- Issue date Feb 6, 2018
- Intel Corporation
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sequencing with coherent and non-coherent sub-systems
- Patent number 9,875,185
- Issue date Jan 23, 2018
- Intel Corporation
- Chunhui Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory fault suppression via re-execution and hardware FSM
- Patent number 9,715,432
- Issue date Jul 25, 2017
- Intel Corporation
- Ramon Matas
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY SEQUENCING WITH COHERENT AND NON-COHERENT SUB-SYSTEMS
- Publication number 20180173628
- Publication date Jun 21, 2018
- Intel Corporation
- CHUNHUI ZHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, METHODS, AND SYSTEMS TO SHARE TRANSLATION LOOKASIDE BU...
- Publication number 20180157598
- Publication date Jun 7, 2018
- Intel Corporation
- CHUNG-LUN CHAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING AN EFFICIENT SCATTER
- Publication number 20160299762
- Publication date Oct 13, 2016
- RAMON MATAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY FAULT SUPPRESSION VIA RE-EXECUTION AND HARDWARE FSM
- Publication number 20160179632
- Publication date Jun 23, 2016
- Intel Corporation
- Ramon MATAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESOLVING MEMORY ACCESSES CROSSING CACHE LINE BOUNDARIES
- Publication number 20160179677
- Publication date Jun 23, 2016
- RAMON MATAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE EVENT HANDLING IN MULTI-THREADED PROCESSOR CORES
- Publication number 20160179533
- Publication date Jun 23, 2016
- Roger Gramunt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SEQUENCING WITH COHERENT AND NON-COHERENT SUB-SYSTEMS
- Publication number 20160011977
- Publication date Jan 14, 2016
- CHUNHUI ZHANG
- G06 - COMPUTING CALCULATING COUNTING

CHUNG-LUN CHAN

Person

Patents Grantslast 30 patents

Resolving memory accesses crossing cache line boundaries

Memory sequencing with coherent and non-coherent sub-systems

Apparatuses, methods, and systems to share translation lookaside bu...

Method and apparatus for performing an efficient scatter

Scalable event handling in multi-threaded processor cores

Memory sequencing with coherent and non-coherent sub-systems

Memory fault suppression via re-execution and hardware FSM

Patents Applicationslast 30 patents

MEMORY SEQUENCING WITH COHERENT AND NON-COHERENT SUB-SYSTEMS

APPARATUSES, METHODS, AND SYSTEMS TO SHARE TRANSLATION LOOKASIDE BU...

METHOD AND APPARATUS FOR PERFORMING AN EFFICIENT SCATTER

MEMORY FAULT SUPPRESSION VIA RE-EXECUTION AND HARDWARE FSM

RESOLVING MEMORY ACCESSES CROSSING CACHE LINE BOUNDARIES

SCALABLE EVENT HANDLING IN MULTI-THREADED PROCESSOR CORES

MEMORY SEQUENCING WITH COHERENT AND NON-COHERENT SUB-SYSTEMS