Chung-Wah Norris Ip

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
System, method, and computer program product for displaying debuggi...
- Patent number 10,783,304
- Issue date Sep 22, 2020
- Cadence Design Systems, Inc.
- Thiago Radicchi Roque
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and computer program product for displaying multipl...
- Patent number 10,635,768
- Issue date Apr 28, 2020
- Cadence Design Systems, Inc.
- Thiago Radicchi Roque
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and computer program product for connectivity ver...
- Patent number 10,409,945
- Issue date Sep 10, 2019
- Cadence Design Systems, Inc.
- Chung-Wah Norris Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and articles of manufacture for X-behavior verifi...
- Patent number 10,380,295
- Issue date Aug 13, 2019
- Cadence Design Systems, Inc.
- Chung-Wah Norris Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method, and computer program product for capture and reuse...
- Patent number 10,331,547
- Issue date Jun 25, 2019
- Cadence Design Systems, Inc.
- Chien-Liang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing selective transformation for low...
- Patent number 10,162,917
- Issue date Dec 25, 2018
- Cadence Design Systems, Inc.
- Fabiano Peixoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and articles of manufacture for graph-driven veri...
- Patent number 10,094,875
- Issue date Oct 9, 2018
- Cadence Design Systems, Inc.
- Chien-Liang Lin
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for automated debugging of a device under test
- Patent number 9,928,328
- Issue date Mar 27, 2018
- Cadence Design Systems, Inc.
- Ynon Cohen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and articles of manufacture for automatic extract...
- Patent number 9,734,278
- Issue date Aug 15, 2017
- Cadence Design System, Inc.
- Victor Markus Purri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and articles of manufacture for trace warping for...
- Patent number 9,659,142
- Issue date May 23, 2017
- Cadence Design Systems, Inc.
- Claudionor Jose Nunes Coelho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Isolating differences between revisions of a circuit design
- Patent number 9,477,802
- Issue date Oct 25, 2016
- Cadence Design Systems, Inc.
- Chung-Wah Norris Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Manipulation of traces for debugging a circuit design
- Patent number 9,081,927
- Issue date Jul 14, 2015
- Jasper Design Automation, Inc.
- Claudionor José Nunes Coelho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Manipulation of traces for debugging behaviors of a circuit design
- Patent number 8,990,745
- Issue date Mar 24, 2015
- Jasper Design Automation, Inc.
- Claudionor José Nunes Coelho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Visualization constraints for circuit designs
- Patent number 8,984,461
- Issue date Mar 17, 2015
- Jasper Design Automation, Inc.
- Chung-Wah Norris Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constraining traces in formal verification
- Patent number 8,863,049
- Issue date Oct 14, 2014
- Jasper Design Automation, Inc.
- Lars Lundgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indexing behaviors and recipes of a circuit design
- Patent number 8,831,925
- Issue date Sep 9, 2014
- Jasper Design Automation, Inc.
- Kathryn Drews Kranen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indexing behaviors and recipes of a circuit design
- Patent number 8,731,894
- Issue date May 20, 2014
- Jasper Design Automation, Inc.
- Kathryn Drews Kranen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Comprehending waveforms of a circuit design
- Patent number 8,630,824
- Issue date Jan 14, 2014
- Jasper Design Automation, Inc.
- Chung-Wah Norris Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Comprehending a circuit design
- Patent number 8,527,911
- Issue date Sep 3, 2013
- Jasper Design Automation, Inc.
- Kathryn Drews Kranen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Comprehending a circuit design
- Patent number 8,458,621
- Issue date Jun 4, 2013
- Jasper Design Automation, Inc.
- Kathryn Drews Kranen
Information Patent Grant
Generalizing and inferring behaviors of a circuit design
- Patent number 8,205,187
- Issue date Jun 19, 2012
- Jasper Design Automation, Inc.
- Claudionor José Nunes Coelho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extracting, visualizing, and acting on inconsistencies between a ci...
- Patent number 7,895,552
- Issue date Feb 22, 2011
- Jasper Design Automation, Inc.
- Vigyan Singhal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing formal verification complexity of designs with multiple re...
- Patent number 7,647,572
- Issue date Jan 12, 2010
- Jasper Design Automation, Inc.
- Chung-Wah Norris Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interactive analysis and debugging of a circuit design during funct...
- Patent number 7,506,288
- Issue date Mar 17, 2009
- Jasper Design Automation, Inc.
- Chung-Wah Norris Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for determining and identifying signals that are...
- Patent number 7,437,694
- Issue date Oct 14, 2008
- Jasper Design Automation
- Lawrence Loh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Meaningful visualization of properties independent of a circuit design
- Patent number 7,421,668
- Issue date Sep 2, 2008
- Jasper Design Automation, Inc.
- Chung-Wah N. Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing formal verification complexity of designs with counters
- Patent number 7,418,678
- Issue date Aug 26, 2008
- Jasper Design Automation, Inc.
- Chung-Wah N Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing formal verification complexity of designs with datapaths
- Patent number 7,237,208
- Issue date Jun 26, 2007
- Jasper Design Automation, Inc.
- Chung-Wah N. Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for identifying design efficiency and effectivene...
- Patent number 7,159,198
- Issue date Jan 2, 2007
- Jasper Design Automation
- Chung-Wah Norris Ip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for guiding and optimizing formal verification fo...
- Patent number 7,065,726
- Issue date Jun 20, 2006
- Jasper Design Automation, Inc.
- Vigyan Singhal
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MANIPULATION OF TRACES FOR DEBUGGING A CIRCUIT DESIGN
- Publication number 20150100932
- Publication date Apr 9, 2015
- Jasper Design Automation, Inc.
- Claudionor José Nunes Coelho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANIPULATION OF TRACES FOR DEBUGGING BEHAVIORS OF A CIRCUIT DESIGN
- Publication number 20150100933
- Publication date Apr 9, 2015
- Jasper Design Automation, Inc.
- Claudionor José Nunes Coelho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VISUALIZATION CONSTRAINTS FOR CIRCUIT DESIGNS
- Publication number 20150095862
- Publication date Apr 2, 2015
- Jasper Design Automation, Inc.
- Chung-Wah Norris Ip
- G06 - COMPUTING CALCULATING COUNTING

Chung-Wah Norris Ip

Person

Patents Grantslast 30 patents

System, method, and computer program product for displaying debuggi...

System, method, and computer program product for displaying multipl...

Methods, systems, and computer program product for connectivity ver...

Methods, systems, and articles of manufacture for X-behavior verifi...

System, method, and computer program product for capture and reuse...

Method and system for implementing selective transformation for low...

Methods, systems, and articles of manufacture for graph-driven veri...

Method and system for automated debugging of a device under test

Methods, systems, and articles of manufacture for automatic extract...

Methods, systems, and articles of manufacture for trace warping for...

Isolating differences between revisions of a circuit design

Manipulation of traces for debugging a circuit design

Manipulation of traces for debugging behaviors of a circuit design

Visualization constraints for circuit designs

Constraining traces in formal verification

Indexing behaviors and recipes of a circuit design

Indexing behaviors and recipes of a circuit design

Comprehending waveforms of a circuit design

Comprehending a circuit design

Comprehending a circuit design

Generalizing and inferring behaviors of a circuit design

Extracting, visualizing, and acting on inconsistencies between a ci...

Managing formal verification complexity of designs with multiple re...

Interactive analysis and debugging of a circuit design during funct...

System and method for determining and identifying signals that are...

Meaningful visualization of properties independent of a circuit design

Managing formal verification complexity of designs with counters

Managing formal verification complexity of designs with datapaths

System and method for identifying design efficiency and effectivene...

System and method for guiding and optimizing formal verification fo...

Patents Applicationslast 30 patents

MANIPULATION OF TRACES FOR DEBUGGING A CIRCUIT DESIGN

MANIPULATION OF TRACES FOR DEBUGGING BEHAVIORS OF A CIRCUIT DESIGN

VISUALIZATION CONSTRAINTS FOR CIRCUIT DESIGNS